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Super junction metal oxide semiconductor field effect transistor (MOSFET) terminal protection structure

A terminal protection structure and super junction technology, which is applied in the direction of electrical components, electric solid devices, circuits, etc., can solve the problems of degraded device performance and achieve the effect of protecting anti-noise and protecting devices

Active Publication Date: 2015-06-03
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, in practical application systems, the interference of external signals is also an important factor that degrades device performance.

Method used

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  • Super junction metal oxide semiconductor field effect transistor (MOSFET) terminal protection structure
  • Super junction metal oxide semiconductor field effect transistor (MOSFET) terminal protection structure

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Embodiment Construction

[0025] The terminal protection structure of the super junction MOSFET described in the present invention is described as follows in conjunction with the accompanying drawings.

[0026] Such as figure 1 As shown, the protection structure includes:

[0027] A heavily doped region 1 of the substrate.

[0028] The epitaxial drift region 2 located on the heavily doped region 1 of the substrate.

[0029] A plurality of semi-insulating column regions 3 arranged horizontally in the epitaxial drift region 2, the semi-insulating column regions 3 can be a single material, or a composite structure of semiconductor insulating material and insulating material.

[0030] An ion-implanted well region 4 is formed on the surface of the epitaxial drift region 2. There are a plurality of semi-insulating column regions 3 below the well region 4. In the right side of the well region 4, there is a P-type heavily doped P-type whose upper surface is located on the device surface. Region 7, the heavi...

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Abstract

The invention discloses a super junction metal oxide semiconductor field effect transistor (MOSFET) terminal protection structure. The structure comprises a substrate heavily doped zone, an epitaxial drift region which is located above the heavily doped zone, and a plurality of insulating column zones which are horizontally arranged and located in the epitaxial drift region. A well zone is formed on the surface of the epitaxial drift region. First polycrystalline silicon grid electrode and second polycrystalline silicon grid electrode are arranged above the well zone, wherein the first polycrystalline silicon grid electrode is the grid of a super junction MOSEFT of a cellular zone, while the second polycrystalline silicon grid electrode is the polycrystalline silicon grid electrode arranged wire on the outer periphery of a supper junction cellular, and is connected to a grid electrode packaging PAD of a product. The first polycrystalline silicon grid electrode is partly located above a field oxide layer, and the second polycrystalline silicon grid electrode arranged wire is completely located above the field oxide layer. The well zone and a contact hole form ohmic contact through a P-type heavily doped zone and the well zone is connected with a metal layer. The metal layer is covered above the second polycrystalline silicon arranged wire, and a layer of middle film is arranged between the metal layer and the second polycrystalline silicon grid electrode arranged wire to separate the metal layer and the second polycrystalline silicon grid electrode arranged wire. The super junction MOSFET terminal protection structure enables the polycrystalline silicon grid electrode arranged wire to be shielded, and a device is better in anti-interference capacity.

Description

technical field [0001] The invention relates to the field of semiconductor device design, in particular to a terminal protection structure of a super junction MOSFET. Background technique [0002] Super junction MOSFET devices are widely used in power electronic systems as power devices. The switching loss of the device is an important indicator of product quality. In order to reduce the loss, the design optimization of mainstream products in the industry mainly focuses on reducing the gate resistance of the product and gate-drain parasitic coupling capacitance. reduction aspect. However, in practical application systems, the interference of external signals is also an important factor that degrades device performance. After the external interference signal is absorbed by the super junction MOSFET device, the self-excitation or coupling effect will cause the product to be restarted when it is turned off, and the driving voltage will be insufficient at the beginning, and the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/58
CPCH01L2924/0002
Inventor 胡晓明
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP