A method for emulating large-capacity memory by imitating netlist after simplifying memory

Abstract

The invention discloses a method for simulating a high-capacity memory by imitating a net list after simplifying the memory. The method includes the steps: 1) setting out a critical path to generate a net list of the critical path; 2) marking a global connecting line on a Memory gds and extracting a net list containing parasitic information of the global connecting line from the Memory gds; 3) back marking capacitance and load for the net list of the critical path by the aid of the net list containing the parasitic information of the global connecting line; 4) extracting resistance information of the global connecting line in the Memory gds; 5) back marking resistance and processing a TT-shaped network for the net list of the critical path; and 6) using a new simplified net list for simulation. On the premise of ensuring simulation precision, the size of the net list is furthest reduced, simulation is greatly accelerated, a large SRAM (static random access memory can be possibly simulated, and software simulation difficulty is reduced.

Description

technical field [0001] The invention relates to a memory simulation method in the design process of a semiconductor MemoryCompiler (storage body compiler software), in particular to a method for realizing large-capacity memory simulation by imitating a netlist after simplifying the memory. Background technique [0002] For a common SOC (System Ona ​​Chip, system-on-a-chip) design, the on-chip memories SRAM, ROM, etc. account for about 20% of the chip area. Most of these on-chip memories are generated with MemoryCompiler. MemoryCompiler can generate Memorycells of different sizes and their models (models) according to customer needs. Among them, the Synopsys (software company name) model requires SRAM timing (timing) information, such as setup / hold (setup time / stop time), delay (Delay), capacitance (capacitance), these must be obtained by simulating the generated SRAM. The simulation must reflect the real timing information of the Memory, and the simulation netlist used mus...

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a method of imitating the netlist after simplifying the memory to realize the simulation of the large-capacity memory, the method realizes the simulation of the large SRAM (memory) by generating the simplified netlist, and solves the problem of large memory in the MemoryCompiler design process. SRAM simulation is difficult, and the simulation speed is improved, and the design risk brought to customers due to the estimation method is reduced.

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