Triple data encryption standard (3DES) encryption algorithm circuit applicable to passive portable equipment

An encryption algorithm and circuit technology, applied in general stored program computer, internal/peripheral computer component protection, etc., can solve the problems of high power consumption, high power consumption of operation, burden of on-chip bus, etc., to reduce area and resource consumption, The effect of reducing dynamic power consumption and simplifying complexity

Active Publication Date: 2013-06-12
INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] First, the 3DES algorithm is characterized by a large amount of calculations and a high degree of parallelism, and most of the operations are logic operations such as permutation, shifting, and XOR. It is inefficient and time-consuming to use the microprocessor to execute instructions serially.
[0006] Second, the CPU card is passive and portable. It obtains energy through electromagnetic induction between the reader and the card reader. The available power is limited. The structure of the microprocessor is complex and the power consumption is large. The long-term high power consumption of 3DES is the card. unbearable in itself
[0007] Third, the microprocessor needs to frequently rely on on-chip ROM and RAM to implement 3DES, which will introduce additional power consumption on the one hand, and on the other hand will also cause a huge burden on the on-chip bus that provides data interaction
[0008] On the other hand, although the above-mentioned problems can be avoided by designing the 3DES algorithm as a hardware coprocessor of the CPU card, the hardware design has a large degree of freedom and strong pertinence. Although different architectures can achieve the same function, their performance parameters are different. Each has its own emphasis, and a hardware structure that does not meet the characteristics of the system requirements will reduce system performance or even cause design failure.
[0009] The characteristic of the CPU card chip is that the operating frequency is not very high (ISO-14443 protocol stipulates that it is 13.56MHz±7kHz), but it has strict requirements for low power consumption design. The advantages of area and low resource consumption, while the general-purpose 3DES hardware circuit structure is generally aimed at pursuing the high-speed data processing capability of the chip, which is poorly targeted and cannot be well applied to passive portable devices such as CPU cards.

Method used

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  • Triple data encryption standard (3DES) encryption algorithm circuit applicable to passive portable equipment
  • Triple data encryption standard (3DES) encryption algorithm circuit applicable to passive portable equipment
  • Triple data encryption standard (3DES) encryption algorithm circuit applicable to passive portable equipment

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Experimental program
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Effect test

Embodiment 1

[0039] In order to verify a kind of function of the circuit structure that is applicable to the 3DES encryption algorithm of CPU card of the present invention, carried out following experiment:

[0040] A random set of plaintext and key inputs are chosen:

[0041] din=0x9ba26cab5d715f65,

[0042] key1=0xb0004d01e1be37b5,

[0043] key2=0x98feb211c096fa8e,

[0044] key3 = 0x764f9365f02cee22.

[0045] After calculation, the ciphertext output encrypted by 3DES should be:

[0046] dout=0x97078658210b6718.

[0047] Utilize the present invention to carry out encryption and decryption to above plaintext and ciphertext respectively, the result is as follows image 3 shown. image 3 It shows part of the input and output signals input to the 3DES encryption algorithm, the part of the input signals from top to bottom are: reset signal, clock signal, encryption and decryption selection signal, start signal, end signal, output data signal. Depend on image 3 It can be seen from the re...

Embodiment 2

[0049] In order to verify the performance of the above-mentioned circuit structure applicable to the 3DES encryption algorithm of the CPU card proposed by the present invention, the following experiment has been carried out: select the software tool Design Compiler of Charter 0.35 μm CMOS process library and Synopsys company under the worst environmental condition WCCOM (voltage=3.0V, temperature=125 ℃) carries out comprehensive evaluation, obtains as follows Figure 4 The evaluation report shown includes: timing evaluation report (top), unit is ns; area evaluation report (middle), unit is gate number; power consumption evaluation report (bottom). The report shows that the invention can at least meet the requirement of 20MHz working frequency, the area is about 8500 gates, and the dynamic power consumption is only 2.44mW at 3V working voltage and 20MHz working frequency, fully meeting the performance requirements of the CPU card.

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Abstract

The invention discloses a triple data encryption standard (3DES) encryption algorithm circuit applicable to passive portable equipment. The 3DES encryption algorithm circuit applicable to the passive portable equipment comprises a global finite state machine, a data initial permutation module, a secret key initial permutation module, a round function module, a subkey generation module and a data inverse permutation module, wherein the global finite state machine is used for controlling the work state of each module in the encryption algorithm circuit; the data initial permutation module is used for finishing initial permutation of data to be encrypted in the 3DES encryption algorithm; the secret key initial permutation module is used for finishing initial permutation of the secret key in the 3DES encryption algorithm; the round function module is used for finishing calculation of the round function in the 3DES encryption algorithm according to the output data of the data initial permutation module and the subkey generation module; the subkey generation module is used for generating the subkey in the 3DES encryption algorithm according to the output data of the secret key initial permutation module; and the data inverse permutation module is used for finishing inverse permutation of the data in the 3DES encryption algorithm according to the calculation result of the round function module to obtain the final encryption / decryption result of the input data.

Description

technical field [0001] The invention relates to the field of SoC digital circuit design, in particular to a 3DES encryption algorithm circuit suitable for passive portable devices such as CPU cards. Background technique [0002] The CPU card is also called a smart card. The integrated circuit in the card is embedded with a microprocessor, which realizes the cooperative work of software and hardware, and greatly improves its logic control and data processing capabilities. This makes the CPU card use a strong encryption algorithm to process transactions. It is possible to encrypt the entire process, and the security performance far exceeds that of the previous logical encryption card. The CPU card also has the characteristics of large user space, fast reading speed, and multi-purpose support for one card, and can be widely used in many fields such as finance, insurance, transportation, and government industries. [0003] The 3DES encryption algorithm is a security variant of ...

Claims

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Application Information

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Patent Type & AuthorityApplications(China)
IPC IPC(8): G06F21/72G06F15/76
Inventor方睿鲁华祥边昳陈旭陈刚葛滨徐露露
OwnerINST OF SEMICONDUCTORS - CHINESE ACAD OF SCI