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Method for testing diffusion of boron to metal or metallic silicide of surface PMOS (p-channel metal oxide semiconductor) polysilicon gate

A metal silicide, surface channel technology, used in the semiconductor field

Active Publication Date: 2015-04-08
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the SIMS (Secondary Ion Mass Spectrometry) commonly used in the industry and the method of comparing the relative capacitance of NMOS / PMOS cannot meet the above requirements at the same time.

Method used

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  • Method for testing diffusion of boron to metal or metallic silicide of surface PMOS (p-channel metal oxide semiconductor) polysilicon gate
  • Method for testing diffusion of boron to metal or metallic silicide of surface PMOS (p-channel metal oxide semiconductor) polysilicon gate
  • Method for testing diffusion of boron to metal or metallic silicide of surface PMOS (p-channel metal oxide semiconductor) polysilicon gate

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0041] An embodiment of the method for determining the diffusion of surface channel PMOS polysilicon gate boron to metal or metal silicide figure 1 shown, including the following steps:

[0042] 1. Utilize the process and parameters of the benchmark MOSFET process to prepare the first NMOS field effect transistor and the first surface channel PMOS field effect transistor; wherein, the NMOS field effect transistor uses N-type polysilicon as the gate electrode, and the PMOS uses boron ( B) P-type polysilicon as gate electrode;

[0043] The second NMOS field effect transistor and the second surface channel PMOS field effect transistor are prepared by using the MOSFET process to reduce the thermal process;

[0044] Compared with the benchmark MOSFET process, the MOSFET process with reduced thermal process has lower temperature and / or shorter time of thermal process after the gate preparation process, and other processes and parameters are the same; the better MOSFET process with re...

Embodiment 2

[0054] Based on Embodiment 1, the benchmark MOSFET process includes the following steps:

[0055] 1. Active region preparation;

[0056] 2. Double well ion implantation;

[0057] 3. Threshold voltage adjustment injection;

[0058] 4. MOS device gate oxide layer growth;

[0059] 5. Gate preparation, wherein the surface channel PMOS gate adopts P-type polysilicon doped with boron (B);

[0060] 6. Polysilicon oxidation;

[0061] 7. Lightly doped drain (LDD) implantation and rapid thermal annealing;

[0062] 8. Silicon nitride or silicon oxide sidewall CVD deposition;

[0063] 9. Source-drain injection and rapid thermal annealing;

[0064] 10. Preparation of self-aligned metal silicide;

[0065] 11. Back metal connection.

[0066] figure 2 Shown is the threshold voltage VTN(A) of the first NMOS field effect transistor and the threshold voltage VTN(B) of the second NMOS field effect transistor. It can be seen that the threshold voltage VTN(A) of the first NMOS field effec...

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Abstract

The invention discloses a method for testing the diffusion of boron to metal or metallic silicide of a surface PMOS (P-channel metal oxide semiconductor) polysilicon gate. The method comprises the following steps of: preparing a first NMOS (N-channel metal oxide semiconductor) field effect transistor and a first surface PMOS field effect transistor by using the process and the parameter of a reference MOSFET (metal-oxide-semiconductor field effect transistor) process; preparing a second NMOS (N-channel metal oxide semiconductor) field effect transistor and a second surface PMOS field effect transistor by adopting the MOSFET process for reducing the thermal process; and comparing the absolute value of the difference Delta VTN of threshold voltages of both the first NMOS field effect transistor and the second NMOS field effect transistor with the absolute value of the difference Delta VTP of the threshold voltages of both the first surface PMOS field effect transistor and the second surface PMOS field effect transistor, wherein if the absolute value of the Delta VTP is less than or equal to the absolute value of the Delta VTN, that no boron can diffuse to the surface PMOS field effect transistor which is prepared by adopting the reference MOSFET process is indicated, and if the absolute value of the Delta VTP is more than the absolute value of the Delta VTN, that the boron can diffuse obviously to the surface PMOS field effect transistor is indicated. The method disclosed by the invention can be used for electrically and quantitatively evaluating the influence of the diffusion of the boron of the surface PMOS polysilicon gate prepared by adopting the reference MOSFET process on a device.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a method for measuring the diffusion of surface channel PMOS polysilicon gate boron to metal or metal silicide. Background technique [0002] With the increasing integration of devices in semiconductor integrated circuit chips, the size of commonly used metal-oxide-semiconductor field effect transistors (MOSFETs) will be further reduced, and lower operating voltages and higher drive currents are required. . [0003] In order to reduce the size of the device and reduce the cost, the industry often adopts the so-called "self-aligned via" (SAC) method; to reduce the operating voltage and increase the drive current, especially for P-channel MOS transistors, it is necessary to use Surface channel (surface channel) devices. However, when the two are combined, there will be special requirements for the gate structure and process: [0004] 1) Perform polysilicon N-type and P-type doping bef...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01N13/00
Inventor 刘剑熊涛孙尧罗啸陈瑜陈华伦
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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