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Etching method for improving step effect of self-aligned silicide block layer

A technology of self-aligned silicide and barrier layer, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as incomplete removal, device failure, source or drain damage, etc., and achieve uniform coverage Effect

Active Publication Date: 2013-09-11
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] According to the manufacturing process of semiconductor devices, after the salicide barrier layer is formed, it must be etched to reach a preset thickness. However, if the conventional etching process is directly performed, due to the existence of the step effect , after etching, the thickness of the top and bottom of the step is still very different. If the thickness of the bottom reaches the preset thickness, the thickness of the top has not yet reached, so that the subsequent process cannot completely remove the self-aligned silicide barrier layer. It makes it impossible to form metal silicide in this area, causing the device to fail; if the thickness of the top reaches the preset thickness, the thickness of the bottom will be smaller than the preset thickness, resulting in damage to the source or drain of the active region, making the device performance Offset design specifications, which will seriously affect the performance of the final device

Method used

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  • Etching method for improving step effect of self-aligned silicide block layer
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  • Etching method for improving step effect of self-aligned silicide block layer

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Embodiment 1

[0031] As mentioned above, regardless of whether the film is deposited by physical vapor deposition or chemical vapor deposition, the step effect problem will inevitably occur in the densely distributed areas of the semiconductor device layer, that is, the thickness of the film in each part of the step is inconsistent, resulting in film coverage Uneven. The product applied by the etching method of the present invention can be any semiconductor device product and can be applied to any semiconductor device layer. The present embodiment of the present invention uses a 55nm high voltage (HV) product and a plasma with a thickness of 600A. Reinforced tetraethoxysilane (PETEOS) deposited silicon dioxide (SiO 2 ) The SAB layer is taken as an example to explain in detail the etching method for improving the step effect of the SAB layer of the present invention, but this is not used to limit the scope of the present invention.

[0032] Combine below Figure 2-5 The etching method for impro...

Embodiment 2

[0044] As mentioned above, regardless of whether the film is deposited by physical vapor deposition or chemical vapor deposition, the step effect problem will inevitably occur in the densely distributed areas of the semiconductor device layer, that is, the thickness of the film in each part of the step is inconsistent, resulting in film coverage Uneven. The product applied by the etching method of the present invention can be any semiconductor device product, and can be applied to any semiconductor device layer. In this embodiment of the present invention, a 55nm complementary metal oxide semiconductor photosensitive device (CMOS image sensor, CIS) product is used. And a 400A silicon-rich oxide (SRO) SiO 2 The SAB layer is taken as an example to explain in detail the etching method for improving the step effect of the SAB layer of the present invention, but this is not used to limit the scope of the present invention.

[0045] The etching method for improving the step effect of t...

Embodiment 3

[0057] As mentioned above, regardless of whether the film is deposited by physical vapor deposition or chemical vapor deposition, the step effect problem will inevitably occur in the densely distributed areas of the semiconductor device layer, that is, the thickness of the film in each part of the step is inconsistent, resulting in film coverage Uneven. The product applied by the etching method of the present invention can be any semiconductor device product, and can be applied to any semiconductor device layer. The present embodiment of the present invention uses a 55nm flash product and a plasma-enhanced four with a thickness of 400A. SiO deposited by ethoxysilane (PETEOS) 2 The SAB layer is taken as an example to explain in detail the etching method for improving the step effect of the salicide barrier layer of the present invention, but this is not used to limit the scope of the present invention.

[0058] The etching method for improving the step effect of the SAB layer on t...

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PUM

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Abstract

The invention provides an etching method for improving the step effect of a self-aligned silicide block layer. The self-aligned silicide block layer is of a silicon oxide type, and the etching method comprises a pretreatment process and a main etching process. The pretreatment process comprises the steps of forming plasma which has isotropic etching capacity, and processing the top portion of a step zone of the self-aligned silicide block layer through selective etching with the plasma which has isotropic etching capacity. The main etching process comprises the steps of forming plasma which has anisotropic etching capacity, and processing the top portion, the side walls and the bottom portion of the step zone of the self-aligned silicide block layer through constant-rate etching almost snychronously with the plasma which has anisotropic etching capacity. By means of the etching method, the step effect of the self-aligned silicide block layer can be eliminated effectively, the self-aligned silicide block layer covers a semiconductor uniformly, and the difficulty in removing the self-aligned silicide block layer in follow-up manufacturing processes is decreased.

Description

Technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to an etching method for improving the step effect of a salicide barrier layer. Background technique [0002] In the semiconductor device manufacturing process, after the semiconductor device layer is formed, metal silicide needs to be formed in a specific area to reduce contact resistance. In this process, it is usually necessary to use a self-aligned silicide block layer (SAB) to protect areas on the semiconductor device layer where metal silicide does not need to be formed. The salicide solutions currently widely used in the industry include a silicon oxide SAB layer and a silicon oxide / silicon nitride combined SAB layer. For the silicon oxide SAB layer solution, the ideal SAB layer film has uniform step coverage, that is, the thickness of each part of the step is uniform, so as to reduce the process difficulty of the subsequent process. [0003] However, with the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/311
Inventor 李程吴敏杨渝书秦伟黄海辉高慧慧
Owner SHANGHAI HUALI MICROELECTRONICS CORP