Etching method for improving step effect of self-aligned silicide block layer
A technology of self-aligned silicide and barrier layer, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as incomplete removal, device failure, source or drain damage, etc., and achieve uniform coverage Effect
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0031] As mentioned above, regardless of whether the film is deposited by physical vapor deposition or chemical vapor deposition, the step effect problem will inevitably occur in the densely distributed areas of the semiconductor device layer, that is, the thickness of the film in each part of the step is inconsistent, resulting in film coverage Uneven. The product applied by the etching method of the present invention can be any semiconductor device product and can be applied to any semiconductor device layer. The present embodiment of the present invention uses a 55nm high voltage (HV) product and a plasma with a thickness of 600A. Reinforced tetraethoxysilane (PETEOS) deposited silicon dioxide (SiO 2 ) The SAB layer is taken as an example to explain in detail the etching method for improving the step effect of the SAB layer of the present invention, but this is not used to limit the scope of the present invention.
[0032] Combine below Figure 2-5 The etching method for impro...
Embodiment 2
[0044] As mentioned above, regardless of whether the film is deposited by physical vapor deposition or chemical vapor deposition, the step effect problem will inevitably occur in the densely distributed areas of the semiconductor device layer, that is, the thickness of the film in each part of the step is inconsistent, resulting in film coverage Uneven. The product applied by the etching method of the present invention can be any semiconductor device product, and can be applied to any semiconductor device layer. In this embodiment of the present invention, a 55nm complementary metal oxide semiconductor photosensitive device (CMOS image sensor, CIS) product is used. And a 400A silicon-rich oxide (SRO) SiO 2 The SAB layer is taken as an example to explain in detail the etching method for improving the step effect of the SAB layer of the present invention, but this is not used to limit the scope of the present invention.
[0045] The etching method for improving the step effect of t...
Embodiment 3
[0057] As mentioned above, regardless of whether the film is deposited by physical vapor deposition or chemical vapor deposition, the step effect problem will inevitably occur in the densely distributed areas of the semiconductor device layer, that is, the thickness of the film in each part of the step is inconsistent, resulting in film coverage Uneven. The product applied by the etching method of the present invention can be any semiconductor device product, and can be applied to any semiconductor device layer. The present embodiment of the present invention uses a 55nm flash product and a plasma-enhanced four with a thickness of 400A. SiO deposited by ethoxysilane (PETEOS) 2 The SAB layer is taken as an example to explain in detail the etching method for improving the step effect of the salicide barrier layer of the present invention, but this is not used to limit the scope of the present invention.
[0058] The etching method for improving the step effect of the SAB layer on t...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 