Transistor formation method and CMOS formation method

Abstract

Provided are a transistor formation method and a CMOS formation method. The transistor formation method comprises: providing a semiconductor substrate which is formed with a gate dielectric layer, a gate electrode layer and a hard mask layer on the surface in sequence, wherein the two sides of the gate dielectric layer, the gate electrode layer and the hard mask layer are formed with first side walls and pseudo side walls in sequence; forming stress liner layers in the semiconductor substrate which is closely next to the two sides of the pseudo side walls; removing the pseudo side walls after the stress liner layers are formed and then forming second side walls on the outside surfaces of the first side walls; performing ion implantation on the stress liner layers after the second side walls are formed and then forming self-aligned silicide layers in the stress liner layers, wherein the surfaces of the self-aligned silicide layers are flush with the surfaces of the stress liner layers; and removing the hard mask layer after the self-aligned silicide layers are formed. With the transistor formation method, mobility of carriers in channel region is enhanced and performance of the transistor is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a transistor and a method for forming a CMOS. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing toward higher component density and higher integration in order to achieve higher computing speed, larger data storage capacity, and more functions. Therefore, gates of complementary metal oxide semiconductor (CMOS) transistors are becoming thinner and shorter than before. However, the size change of the gate will affect the electrical performance of semiconductor devices. At present, the performance of semiconductor devices is mainly improved by controlling the carrier mobility. A key element of the technology is controlling the stress in the transistor channel. For example, by properly controlling the stress and increasing the mobility of carriers (electro...

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Problems solved by technology

[0011] However, the transistor with the stress liner layer formed by the prior art provides limited stress to the channel region, and the improvement of the carrier mobility of the channel region is small, resulting in a limited improvement in the performance of the formed transistor.

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