Ripple reducing circuit for light-load pulse hopping mode of DC-DC (Direct Current-Direct Current) converter
A converter and pulse-skipping technology, which is applied in the field of electronic circuits, can solve the problems of small output voltage ripple, large output voltage ripple, and high conversion efficiency, and achieve reduced output voltage ripple, peak value reduction, and high conversion efficiency effect
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Embodiment 1
[0039] refer to figure 1 , the present invention is used in the ripple reduction circuit of DC-DC converter light load pulse skip mode, including capacitor charging and discharging unit 1, comparison unit 2, logic control unit 3 and on-time control unit 4. in:
[0040] Capacitor charging and discharging unit 1, according to the switch off signal ZC generated inside the converter, charges or discharges the capacitor to obtain voltage signals V of different sizes C1 output to comparison unit 2;
[0041] The comparison unit 2 has three input terminals A, B, C and one output terminal D; wherein the first input terminal A is connected to the reference voltage VR1 generated inside the converter, and the second input terminal B is connected to the reference voltage VR2 generated inside the converter , the third input terminal C is connected to the voltage signal V input by the capacitor charging and discharging unit 1 C1 ; Its output terminal D outputs the control signal RR_CTL to...
Embodiment 2
[0074] The capacitor charging and discharging unit 1 , the logic control unit 3 and the conduction time control unit 4 of the present invention are the same as those in the first embodiment.
[0075] refer to Figure 5 , the comparison unit 2 of the present invention includes two low-voltage PMOS transistors M 601 and M 602 , 3 low-voltage NMOS tubes M 603 ~ M 605 , 2 transmission gates TG 3 ~TG 4 , 2 inverters INV8~INV9;
[0076] The 2 transmission gates TG 3 ~TG 4 , its output terminal is connected and outputs the reference voltage V 2 , the third transmission gate TG 3 The input end of the converter is connected to the reference voltage VR1 generated inside the converter, and the fourth transmission gate TG 4 The input end of the converter is connected to the reference voltage VR2 generated inside the converter;
[0077] The low voltage PMOS tube M 601 and M 602 Form a differential pair structure, its source is connected and connected to the bias current I gene...
Embodiment 1 and Embodiment 2
[0082] In conjunction with embodiment 1 and embodiment 2, the working principle of the present invention is:
[0083] When the load of the converter is light, the converter works in skip cycle mode, the switching tube shutdown signal ZC is logic high level, and the first capacitor C inside the capacitor charging and discharging unit 1 1 start charging, the voltage signal V C1 Gradually increases, the voltage signal V C1 When it rises to the reference voltage VR1, the control signal RR_CTL output by the comparison unit 2 becomes a logic high level, and the frequency divider 31 starts counting the pulse signal LG of the lower switching tube of the converter. If the load is light enough, the frequency divider 31 counts After 16 cycles, the pulse counting signal CONT is turned to a high level, and the switch signal RR output by the logic synthesis module 32 is also turned to a logic high level at this time, and the conduction time control unit 4 is controlled to supply a large cu...
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