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Low-k intermetallic dielectric (Low-k IMD) layer etching method

An inter-metal dielectric layer, low dielectric constant technology, applied in circuits, electrical components, semiconductor/solid-state device manufacturing, etc., can solve problems such as Low-kIMD damage, and achieve the effect of eliminating damage

Active Publication Date: 2014-01-15
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0021] The problem with the process step of etching vias and trenches in Low-k IMD is that because of the loose and porous nature of Low-k IMD, the above wet cleaning step will damage the Low-k IMD causes damage

Method used

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  • Low-k intermetallic dielectric (Low-k IMD) layer etching method
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  • Low-k intermetallic dielectric (Low-k IMD) layer etching method

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specific Embodiment 1

[0047] combine Figure 9~15 Description such as Figure 8 The specific steps of etching through holes and grooves in the shown embodiment of the present invention-Low-k IMD layer are as follows:

[0048] Step 801, Figure 9 It is a schematic diagram of the cross-sectional structure of the step 801 of etching vias and trenches in the Low-k IMD layer of the present invention, as Figure 9 As shown, an etch stop layer 300 and a Low-k intermetal dielectric (IMD) layer 301 are sequentially deposited on the first metal interconnection layer; in this step, a wafer is provided, and the wafer has the first metal interconnection layer ; In this embodiment, only the first metal interconnection layer is taken as an example to illustrate the metal interconnection method of the present invention, and the first metal interconnection layer shown can be any metal interconnection layer in practical applications. The material of the etching stop layer 300 is silicon carbonitride (SiCN), and t...

specific Embodiment 2

[0071] combine Figure 17~19 Description such as Figure 16 The specific steps of etching through holes and trenches in the Low-k IMD layer of the second embodiment of the present invention are shown, wherein, steps 1001 to 1004 of the second embodiment of the present invention and steps 801 to 804 of the first embodiment of the present invention Same, no more details.

[0072] Step 1005, Figure 17 It is a schematic cross-sectional structure diagram of the manufacturing step 1005 of etching via holes and trenches in the Low-k IMD of the second embodiment of the present invention, as Figure 17 As shown, the Low-k intermetallic dielectric layer 301 is etched to form trenches and via holes with the hard mask as a shield, and stop on the etching stop layer;

[0073] In this step, the method for etching the Low-k intermetallic dielectric layer 301 is dry etching, and the end point detection method is used to control the stop of etching, and the etching stop layer 300 is used a...

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Abstract

The invention provides a low-k intermetalic dielectric (Low-k IMD) layer etching method. According to the method, after a through hole and a groove are formed in the Low-k IMD layer in an etching mode, a wafer with the through hole and the groove is taken out from an etching reaction cavity in an air-isolated environment and placed in a reaction cavity for atomic layer recovery, Low-k intermetallic dielectric recovery layers are formed at least on the surface of the through hole and the surface of the groove through atomic layer recovery, and damage to the Low-k IMD layer in the forming process of the through hole and the groove is eliminated.

Description

technical field [0001] The invention relates to a semiconductor manufacturing method, in particular to a Low-k intermetal dielectric layer etching method. Background technique [0002] With the development of semiconductor manufacturing technology, the area of ​​semiconductor chips is getting smaller and smaller, and at the same time, the number of semiconductor devices on a semiconductor chip is also increasing. The metal interconnection layer connects the semiconductor devices to each other to realize signal transmission between the semiconductor devices, forming a semiconductor circuit. The metal interconnection layer is composed of high-density metal wires and an inter-metal dielectric (Inter-metal Dielectric, IMD) between the metal wires. In the manufacture of large-scale integration (VLSI) and ultra-large-scale integration (ULSI), multiple metal interconnection layers are fabricated above the semiconductor device, and the fabrication process is also called metal inter...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768
CPCH01L21/76802H01L21/76814
Inventor 王新鹏张海洋
Owner SEMICON MFG INT (SHANGHAI) CORP
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