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Formation method of semiconductor structure

A semiconductor and dielectric layer technology, applied in the field of semiconductor structure formation, can solve the problems of semiconductor structure cost increase, unfavorable process cost control, etc., and achieve the effect of improving manufacturability, reducing process difficulty and manufacturing cost

Active Publication Date: 2016-08-10
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] In addition, the formation of the surface pattern of the dielectric layer by the double pattern exposure process or the multiple pattern exposure process will lead to an increase in the cost of forming a semiconductor structure, which is not conducive to process cost control

Method used

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  • Formation method of semiconductor structure
  • Formation method of semiconductor structure
  • Formation method of semiconductor structure

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Experimental program
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Embodiment 1

[0033] Attached below Figure 2 to Figure 7 A method for forming a semiconductor structure in an embodiment of the present invention will be described in detail.

[0034] refer to figure 2 , a substrate 201 is provided, and the substrate 201 includes two regions, a first region 2011 and a second region 2012 .

[0035] In this embodiment, the material of the substrate 201 is single crystal silicon or single crystal silicon germanium, or single crystal carbon-doped silicon; or may also include other materials, which are not limited in the present invention.

[0036] In addition, a device structure (not shown) is formed in the substrate 201, and the device structure may be a device structure formed in the semiconductor front-end process, such as a MOS transistor; the substrate 201 may also include a Electrically connected metal interconnect lines.

[0037] refer to image 3 , forming a first dielectric layer 203 on the surface of the substrate 201;

[0038] In this embodime...

Embodiment 2

[0069] Attached below Figure 8 ~ Figure 15 A method for forming a semiconductor structure in another embodiment of the present invention will be described in detail.

[0070] refer to Figure 8 , a substrate 301 is provided, and the substrate 301 includes two regions, a first region 3011 and a second region 3012 .

[0071] In this embodiment, the material of the substrate 301 is single crystal silicon or single crystal silicon germanium, or single crystal carbon-doped silicon; or may also include other materials, which are not limited in the present invention.

[0072] In addition, a device structure (not shown) is formed in the substrate 301, and the device structure may be a device structure formed in the semiconductor front-end process, such as a MOS transistor; the substrate 301 may also include a Electrically connected metal interconnect lines.

[0073] refer to Figure 9 , forming a first dielectric layer 303 on the surface of the substrate 301 .

[0074] In this e...

Embodiment 3

[0090] Attached below Figure 16 ~ Figure 23 A method for forming a semiconductor structure in an embodiment of the present invention will be described in detail.

[0091] refer to Figure 16 , a substrate 401 is provided, and the substrate 401 includes two regions, a first region 4011 and a second region 4012 .

[0092] In this embodiment, the material of the substrate 401 is single crystal silicon or single crystal silicon germanium, or single crystal carbon-doped silicon; or may also include other materials, which are not limited in the present invention.

[0093] In addition, a device structure (not shown) is formed in the substrate 401, and the device structure may be a device structure formed in the semiconductor front-end process, such as a MOS transistor; the substrate 401 may also include a Electrically connected metal interconnect lines.

[0094] refer to Figure 17 , forming a first dielectric layer 403 on the surface of the substrate 401;

[0095] In this embo...

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Abstract

A forming method of a semiconductor structure includes providing a substrate which comprises a first region and a second region; forming a first dielectric layer on the surface of the substrate; forming a first plug penetrating the thickness of the first dielectric layer in the first dielectric layer above the first region; forming a second dielectric layer on the first dielectric layer and the surface of the first plug in the first dielectric layer; forming a first metal interconnection layer penetrating the thickness of the second dielectric layer and connected with the first plug above the first region; forming N-2 dielectric layers on the second dielectric layer and the surface of the first metal interconnection layer in the second dielectric layer sequentially from bottom to top; forming a second plug penetrating the thickness from the first dielectric layer to the Nth dielectric layer above the second region; wherein N is a positive integer larger than 2. The forming method of the semiconductor structure reduces density of photo-etching patterns and times of photo-etching and corrosion, and further reduces process cost.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] As the manufacture of integrated circuits develops toward ultra-large scale integration (ULSI), the feature size (Critical Dimension, CD) of semiconductor devices is getting smaller and smaller, and the integration level of chips is getting higher and higher. In order to improve the integration of devices, the current semiconductor chip usually includes several layers of semiconductor structures, and the semiconductor structures located in different layers are connected by setting via holes or metal interconnection lines between layers to form a chip with specific functions. . [0003] In the existing technology, there are mainly two types of through holes used to realize the connection of different layers of semiconductor structures. One is the first type of through hole that only ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
CPCH01L21/76802H01L21/76832
Inventor 王文博
Owner SEMICON MFG INT (SHANGHAI) CORP