Wafer level packaging method for micro electromechanical system (MEMS) chip and single-chip micro-miniature type MEMS chip

A wafer-level packaging, ultra-small technology, applied in the field of single-chip ultra-small MEMS chips, can solve the problems of large chip area, high cost, low efficiency, etc., and achieve the effect of reducing area, low cost and simple process flow

Inactive Publication Date: 2014-02-05
ANHUI BEIFANG XINDONG LIANKE MICROSYST TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this method is inefficient, resulting in large chip area and high cost

Method used

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  • Wafer level packaging method for micro electromechanical system (MEMS) chip and single-chip micro-miniature type MEMS chip
  • Wafer level packaging method for micro electromechanical system (MEMS) chip and single-chip micro-miniature type MEMS chip
  • Wafer level packaging method for micro electromechanical system (MEMS) chip and single-chip micro-miniature type MEMS chip

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0041] (1) Formation of TSV wafers:

[0042] The material of the first wafer 21 is heavily doped single crystal silicon with a resistivity of about 0.01 Ω·cm, which is a good conductive material. Such as figure 2 As shown, grooves 211' are formed on the first wafer 21 through semiconductor processing processes such as glue coating, exposure, development, etching, and glue removal. The depth of the grooves 211' is 50 μm, and the cross-sectional pattern of the grooves 211' is circular ;

[0043] The insulating material silicon dioxide is filled in the groove 211' by chemical vapor deposition, and then the insulating material outside the groove 211' is removed by reverse etching, so that only the insulating material is arranged in the groove 211', such as image 3 As shown; then, the upper cavity 209a is etched by common semiconductor processing technology, and the depth of the upper cavity 209a is 1 μm; when the upper cavity 209a is etched, a part is left unetched in the mid...

Embodiment 2

[0061] (1) Formation of TSV wafers:

[0062] The material of the first wafer 21 is heavily doped single crystal silicon with a resistivity of about 0.01 Ω·cm, which is a good conductive material. Such as figure 2 As shown, grooves 211' are formed on the first wafer 21 through semiconductor processing processes such as glue coating, exposure, development, etching, and glue removal. ;

[0063] Deposit the insulating material silicon dioxide in the groove 211' by filling the glass paste, then remove the insulating material outside the groove 211', heat and sinter, so that only the insulating material is in the groove 211', such as image 3 As shown; then, the upper cavity 209a is etched by common semiconductor processing technology, and the depth of the upper cavity 209a is 5 μm; when the upper cavity 209a is etched, a part is left unetched in the middle to form a bond The blocks 210 are combined to form a TSV wafer 22 .

[0064] (2) Formation of the first bonded wafer: ...

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Abstract

The invention discloses a wafer level packaging method for a micro electromechanical system (MEMS) chip and a single-chip micro-miniature type MEMS chip. The method comprises the steps of forming a silicon through-hole wafer, forming a first bonded wafer, forming a cover plate wafer, forming a second bonded wafer, forming an MEMS wafer and forming the single-chip micro-miniature type MEMS chip. According to the method, by reducing the depth of an upper cavity, part of a silicon through-hole layer can directly serve as a vertical electrode, and the process is simple. By additionally arranging a metal shielding layer, the influence on the performance of the MEMS chip caused by an environment interference signal is reduced. The prepared single-chip micro-miniature type MEMS chip is small in size and high in yield. By virtue of the metal shielding layer on the chip, the influence on the performance of the MEMS chip caused by the environment interference signal and packaging stress can be reduced.

Description

technical field [0001] The invention belongs to the field of chip packaging, and in particular relates to a MEMS chip wafer-level packaging method, and also relates to a single-chip ultra-small MEMS chip prepared by the method. Background technique [0002] Electronic packaging is to electrically connect one or more electronic component chips to each other, and then encapsulate them in a protective structure. Its purpose is to provide electrical connection, mechanical protection, chemical corrosion protection, etc. for electronic chips. For some electronic products, the surface of the chip cannot be in contact with the packaging material, especially for those MEMS devices with movable structures, which need to be hermetically packaged with ceramic shells, metal shells, preformed plastic shells, etc., but these Packaging methods are costly and bulky, making them unsuitable for use in consumer electronics. As MEMS devices become more widely used in the consumer space, low-cos...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B81C1/00B81C3/00B81B7/00B81B7/02
Inventor 华亚平
Owner ANHUI BEIFANG XINDONG LIANKE MICROSYST TECH
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