Electrostatic discharge resistant LDMOS device

Abstract

The invention relates to an electrostatic discharge resistant LDMOS device, and belongs to the technical field of electronics. A low voltage P well is added in a partial region of a side under a drain terminal of a conventional LDMOS device, and a parasitic N-P-N-P-N structure exists in the LDMOS device, and therefore a low-conducting impedance current discharge path is added. The parasitic N-P-N-P-N structure is equivalent to a structure designed in way that a BJT is connected in series with a SCR and is triggered through high electric field transfer induced by the Kirk effect, and a hole current of an anode of the SCR is largely provided by avalanche breakdown of a reverse-biased PN junction, therefore, the low-conducting impedance current discharge path is added under the condition that extra masking plates are not added, so that the electrostatic discharge (ESD) resistance of the device is improved. The Vhold of the electrostatic discharge resistant LDMOS device is lower than that of the conventional LDMOS device, but the failure current It2 of the electrostatic discharge resistant LDMOS device is higher.

Description

technical field [0001] The invention belongs to the field of electronic technology, and relates to an electrostatic discharge (ESD for short) protection circuit design technology for a semiconductor integrated circuit chip, in particular to an nLDMOS structure embedded with N-P-N-P-N for ESD protection. Background technique [0002] Electrostatic discharge is an unavoidable phenomenon during the production, packaging, and testing of integrated circuit chips. If there is no electrostatic protection device, when electrostatic discharge occurs, a large ESD current will flow through the internal circuit of the chip, causing damage to the components of the internal circuit, resulting in chip failure. As the size of the integrated circuit process becomes smaller and the development of various advanced processes, chips are more likely to be damaged by ESD phenomena. Therefore, the design of anti-ESD has been paid more and more attention. [0003] In the field of intelligent power ...

AI Technical Summary

Problems solved by technology

Although the LDMOS device at the output end has a large area, due to the high electric field transfer caused by the Kirk effect, the LDMOS power transistor has a strong snapback (foldback) effect, which leads to uneven turn-on and current concentration of the parasitic BJT of its multi-finger structure, making its ESD Low performance, easily damaged by ESD phenomena

[0004] In order to increase the anti-ESD capability of LDMOS devices, a figure 2 LDMOS-SCR device shown, the device is equivalent to the figure 1 A P+ injection region is added to the drain end of the traditional LDMOS device shown to form a thyristor structure (also known as a thyristor, abbreviated as SCR in English). The breakdown of the reverse PN junction in the SCR is used to trigger the SCR to turn on, thereby forming a low impedance. The leakage path, the anti-ESD ability is greatly improved, but its maintenance voltage Vhold is significantly lower than that of LDMOS, and the latch-up phenomenon is prone to occur

Images