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Semiconductor device and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve problems such as increasing the difficulty of circuit design, reducing circuit reliability, fluctuating semiconductor device performance stability and reliability, etc. , to avoid the impact of stability and reliability, reduce the difficulty of integration, and avoid the effect of difficult circuit design

Active Publication Date: 2014-03-26
SHANGHAI BEILING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, these methods will increase the difficulty of circuit design and reduce the reliability of circuit work.
At the same time, due to the introduction of the equivalent inductance of the bonding wire, the fluctuation of its process will have a great impact on the stability and reliability of the semiconductor device performance

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

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Effect test

no. 1 approach

[0042] Figure 4 is a schematic cross-sectional view of a partial region of the first embodiment of the semiconductor device of the present invention. This implementation structure is applicable to the case where the input or output terminal of the active area part of the original chip is located on the upper surface of the chip. The first plate 10 is connected to the input or output pin of the package pin of the semiconductor device through the lead-out pin 101 , and the second plate 20 is connected to the base 5 connected to the ground terminal in the package frame of the semiconductor device.

[0043] The equivalent circuit diagram of this connection is shown in Figure 5 As shown, it is equivalent to connecting a capacitor in parallel at the input or output terminal of the semiconductor device, so as to realize the matching of the input or output impedance of the active region of the semiconductor device to the target input or output impedance.

no. 2 approach

[0045] Figure 6It is a schematic cross-sectional view of a partial region of the second embodiment of the semiconductor device of the present invention. This implementation structure is applicable to the case where the input or output terminal of the active area part of the original chip is located at the bottom of the chip. In this embodiment, the first pole plate 10 is electrically isolated from the part of the metal interconnection layer 3 located in the active region, the first pole plate 10 is connected to the ground terminal of the semiconductor device through the lead-out pin 101, and the second pole plate 20 is connected to the ground terminal of the semiconductor device. The dies 5 connected to the input or output terminals in the package frame of the semiconductor device are connected.

[0046] The equivalent circuit diagram of this connection is shown in Figure 7 As shown, it is equivalent to connecting a capacitor in series with the input or output terminal of ...

no. 3 approach

[0048] Figure 8 is a schematic cross-sectional view of a partial region of the third embodiment of the semiconductor device of the present invention. In this embodiment, the input or output terminal of the semiconductor in the active area is located at the bottom of the chip, and the first plate 10 is electrically isolated from the part of the metal interconnection layer 3 located in the active area. The pins 101 are connected to the input or output pins of the package pins of the semiconductor device, and the second plate 20 is connected to the crystal seat 5 in the package frame of the semiconductor device, which keeps the potential floating. In this embodiment, the crystal seat 5 may also be connected to a predetermined terminal, such as a DC bias terminal.

[0049] The equivalent circuit diagram of this connection is shown in Figure 9 As shown, it is equivalent to connecting a capacitor in series with the input or output terminal of the semiconductor device, so as to r...

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PUM

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Abstract

The invention discloses a semiconductor device, which comprises a substrate, an insulating layer, at least one metal interconnection layer and at least one metal layer, wherein the insulating layer is formed on the upper surface of the substrate; the metal interconnection layer is formed on the insulating layer; the metal layer is formed on the lower surface of the substrate. In the semiconductor device, at least one metal layer is formed on the lower surface of the substrate to form a plate capacitor with the metal interconnection layer formed on the upper surface of the substrate, and the plate capacitor is connected to the input or output end of the semiconductor device, thereby realizing matching of the input or output impedance of the semiconductor device with target resistance. The invention further provides a manufacturing method of the semiconductor device. By adopting the method, the impedance matching of the input or output end of the semiconductor device can be realized conveniently and efficiently.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof. Background technique [0002] When a semiconductor device is used in a radio frequency power amplifier circuit or some other specific circuits, it is required to have a high input and output impedance. However, the input and output impedance of many semiconductor devices currently manufactured is very low, so it is necessary to perform impedance matching on these semiconductor devices. The device is connected to a capacitor and packaged together. However, these methods will increase the difficulty of circuit design and reduce the reliability of circuit work. At the same time, due to the introduction of the equivalent inductance of the bonding wire, the fluctuation of its process will have a great impact on the stability and reliability of the performance of the semiconductor device. Contents of the invention [0003] In...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L23/64H01L23/495
CPCH01L2224/48091H01L2924/3011H01L2924/00014H01L2924/00H01L23/642
Inventor 林敏之陈铭陈伟徐维赖海波
Owner SHANGHAI BEILING
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