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CSTBT manufacturing method

A manufacturing method and drift region technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of increasing process cost and improving process difficulty, and achieve the effect of reducing the difficulty of manufacturing process and reducing manufacturing cost

Inactive Publication Date: 2014-04-09
UNIV OF ELECTRONICS SCI & TECH OF CHINA +1
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  • Application Information

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Problems solved by technology

Therefore, the traditional method increases the difficulty of the process and increases the cost of the process

Method used

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Examples

Experimental program
Comparison scheme
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Embodiment

[0126] Taking the manufacturing process of 600V CSTBT as an example, the specific process is as follows:

[0127] (1) Preparation of P + Single crystal silicon wafer 1 substrate material, such as Figure 4 As shown, P + The thickness of the monocrystalline silicon wafer 1 lining is 400-600 μm, the resistivity is 0.0135-0.0375Ω·cm, and the impurity is boron;

[0128] (2) Epitaxial growth of N-type field stop region 2, such as Figure 5 As shown, the thickness of the N-type field stop region 2 is 2 μm, the resistivity is 0.08-0.14 Ω·cm, the growth temperature is 1000-1200° C., and the impurity is phosphorus;

[0129] (3) Epitaxial growth of N - Drift Zone 3, such as Figure 6 Shown, N - The drift region 3 is grown at 1000-1200°C, the impurity is phosphorus, the resistivity is 43.4-86.5Ω·cm, and the thickness is 50μm;

[0130] (4) Growth field oxide layer 4, such as Figure 7 As shown, the growth temperature is 1000-1200 °C, and the thickness is 0.5-1.5 μm;

[0131] (5) Et...

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Abstract

The invention relates to the semiconductor technology, in particular to a CSTBT manufacturing method. According to the basic technology of a CSTBT manufacturing method, an N-type field cut-off region 2 and an N-drifting region 3 are sequentially grown epitaxially on a P+ monocrystalline silicon wafer substrate; after a front face groove-gate MOS technology is formed, the back face is thinned. According to the main technical scheme, selective injection and low temperature annealing are performed on the back face H+ of the wafer, donors relevant to hydrogen are activated, and an N-type CS layer located at the bottom of the Pbody base region is formed. Finally, the back face metallization technology is applied, and then a complete structure of a CSTBT is formed. The CSTBT manufacturing method has the advantages of reducing manufacturing technological difficulty and lowing manufacturing cost and particularly for manufacturing the CSTBT.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a method for manufacturing a CSTBT. Background technique [0002] IGBT (Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor) is a voltage-controlled MOS / BJT composite semiconductor power device. Structurally, the IGBT only adjusts the N+ substrate of the VDMOS to a P+ substrate, but the conductance modulation effect introduced overcomes the contradiction between the inherent on-resistance and the breakdown voltage of the VDMOS itself, so that the IGBT has both bipolar power transistors It has the characteristics of low conduction voltage and large current capacity, and has the advantages of high input impedance of power MOSFET and simple driving circuit. It is precisely because of the above advantages that it has been widely used, such as: new energy technology, advanced transportation tools represented by bullet trains and high-speed rail, hybrid vehicles, household ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/331
CPCH01L29/66325
Inventor 李泽宏宋文龙邹有彪宋洵奕吴明进张金平任敏
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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