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Digital image filter circuit design method based on FPGA evolutionary learning

A filter circuit and design method technology, applied in the field of image processing, can solve problems such as obvious noise, difficult circuit, no consideration of circuit competition and risk, etc., to achieve good visual effect and improved performance

Active Publication Date: 2014-07-23
SUZHOU UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the evolutionary filter circuit method proposed by Sekanina and Vasicek is based on the single-objective evolution with the smallest mean absolute error, which easily ignores the number of large noise points in the image, making some areas of the image noisy, and they do not consider the competition and risk of the circuit problems, making it difficult to apply the evolved circuits in practice

Method used

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  • Digital image filter circuit design method based on FPGA evolutionary learning
  • Digital image filter circuit design method based on FPGA evolutionary learning
  • Digital image filter circuit design method based on FPGA evolutionary learning

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0037] Embodiment one: see figure 1 As shown, a digital image filter circuit design method based on FPGA evolutionary learning, including the evolutionary learning stage and the filter circuit hardware implementation stage, the specific steps are as follows:

[0038] (1) Gene expression is used to encode circuits, and each evolutionary circuit has 9 inputs (3 3 filtering window pixels), the circuit is composed of bit logic function modules, and there are 29 function modules in total, as shown in Table 1:

[0039] Table 1 Definition of circuit function characters

[0040]

[0041] The evolutionary circuit is coded as a string expression, which is composed of function characters and terminal characters, and the terminal characters are denoted as ,Right now ~ , representing the 9 inputs of the circuit, the function character is denoted as , namely in Table 1 ~ . A string expression represents a circuit. The expression structure is divided into a head and a tail....

Embodiment 2

[0059] Embodiment 2: Gaussian white noise with a variance of 0.04, 0.06 and 0.08 is loaded to 13 standard pictures for learning, the obtained circuit is tested on the sailboat picture, and the peak signal-to-noise ratio PSNR and The minimum mean square error MSE is shown in Table 2:

[0060] Table 2 Peak Signal-to-Noise Ratio / Mean Square Error (PSNR / MSE) of image filtering with different concentrations of Gaussian noise

[0061]

[0062] see Figure 4 as shown, Figure 4 (a) is Gaussian noise (D=0.08) sailboat image, Figure 4 (b) is an evolutionary filter (single target) image, Figure 4 (c) is an evolutionary filtering (multi-objective) image, Figure 4 (d) is the frost filtered image, Figure 4 (e) for Lee filtering, Figure 4 (h) Filtering images for wavelets.

[0063] From Table 2 and Figure 4 It can be seen that under Gaussian noise, the difference between multi-objective evolution and other methods is small, but the color is more vivid. The average filterin...

Embodiment 3

[0064] Embodiment 3: load salt and pepper noise with variances of 0.12, 0.16 and 0.2 to 13 standard pictures for learning, and the obtained circuit is tested on the lenna picture, and the peak signal-to-noise ratio (PSNR) and minimum average value of the circuit for the salt and pepper noise and the lenna picture are obtained. The variance MSE is shown in Table 3:

[0065] Table 3 Peak Signal-to-Noise Ratio / Mean Square Error (PSNR / MSE) of Image Filtering for Each Concentration of Salt and Pepper Noise

[0066]

[0067] see Figure 5 as shown, Figure 5 (a) is the salt and pepper noise (D=0.2) lenna image, Figure 5 (b) is an evolutionary filter (single target) image, Figure 5 (c) is an evolutionary filtering (multi-objective) image, Figure 5 (d) is the frost filtered image, Figure 5 (f) is kuan filtered image, 5(g) is 5 5 mean filtered image.

[0068] From Table 3 and Figure 5 It can be seen that under salt and pepper noise, the PSNR of the filter circuit is sm...

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Abstract

The invention discloses a digital image filter circuit design method based on FPGA evolutionary learning. Characteristic optimization is carried out a circuit code and a (2+lambda) evolutionary strategy (ES) by means of a gene expression, a proper relation operation set is evolved through a multi-target model through effect learning before filtering of sample images and after filtering of the sample images, an image filtering effect can be obtained through a filter circuit designed in the mode as good as possible, in a learning phase, a filter can obtain an optimized logic composition structure after definitive evolutionary algebra, and a hardware circuit with image filtered is achieved on an FPGA chip through VHDL conversion and competition and hazard elimination design. According to the method, the non-linear filter circuit is obtained through evolution, so that filtered images are clear and edges of the images are clear.

Description

technical field [0001] The invention belongs to the technical field of image processing, in particular to a digital image filter circuit design method, in particular to a filter circuit design method based on FPGA evolutionary learning. Background technique [0002] Digital image filtering has always been a necessary link in the research of image preprocessing, and the existing research results are mainly on the improvement of algorithms. Among them, the median filter is a nonlinear filter, which can better retain the details and edges of the image and weaken the blurring effect; the Frost filter algorithm assumes that the image is a stationary process, and its impulse response is a bilateral exponential function; Kuan The filtering algorithm assumes that the noise is additive noise related to the signal, and then uses the minimum variance estimation to obtain the linear combination of the observed intensity and the local average intensity in the fixed window; Lee filtering ...

Claims

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Application Information

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IPC IPC(8): H04N5/21
Inventor 陶砚蕴张宇祯郑建颖杨勇朱忠奎
Owner SUZHOU UNIV
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