Method for manufacturing double-layer high-K dielectric structure

Abstract

The invention provides a method for manufacturing a double-layer high-K dielectric structure. The method comprises the step S01 that a semiconductor substrate is provided, and spaced shallow trench isolations are arranged on the semiconductor substrate, the step S02 that the semiconductor substrate is exposed to hafnium-based compounds and steam in a circulating mode to form a first hafnium oxide layer of the preset thickness, the step S03 that the first hafnium oxide layer is exposed to the hafnium-based compounds and strong oxidants in a circulating mode to form a second hafnium oxide layer of the preset thickness, and the step S04 that a metal gate material layer is formed on the surface of the second hafnium oxide layer. According to the method for manufacturing the double-layer high-K dielectric structure, on the one hand, the thickness of silicon oxide on the surface of the semiconductor substrate is reduced, and the EOT parameter of gate dielectrics is within the reasonable range; on the other hand, the second hafnium oxide layer has fewer oxygen vacancies, and the current leakage phenomenon of the finally-formed hafnium oxide dielectric layer is controlled.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits and its manufacture, in particular to a method for manufacturing a double-layer high-K dielectric structure. Background technique [0002] The main device in an integrated circuit, especially a VLSI, is a metal oxide semiconductor field effect transistor (MOS transistor for short). Since the MOS tube was invented, its geometric size has been continuously reduced, and its characteristic size has entered the range of 45nm at present. At this size, fundamental limitations and technical challenges begin to emerge, and further device scaling is becoming increasingly difficult. Among them, in the preparation of MOS transistor devices and circuits, the most challenging thing is that in the process of shrinking traditional CMOS devices, the thickness of the gate oxide layer in the polysilicon / SiO2 structure or polysilicon / SiCN structure is reduced. leakage current. [0003] To this end,...

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Problems solved by technology

In order to reduce the thickness of the silicon oxide layer 300, water vapor with weak oxidizing properties can be selected as the oxidizing agent, but water vapor will cause oxygen vacancies, resulting in increased gate leakage current of hafnium oxide

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