SOI LDMOS device with extending gate structure
A technology for extending gates and devices, applied in the field of semiconductor power devices, can solve problems such as uneven distribution of parasitic resistance and uneven temperature distribution, and achieve the effects of improving device withstand voltage, stable device operation, and uniform temperature distribution
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Example Embodiment
[0025] Example 1
[0026] Figure 4a A cross-sectional view of the structure of a typical extended gate SOI LDMOS device is given. It includes a vertical bottom-up substrate layer 1, a dielectric buried layer 2 and a first conductive type semiconductor active layer 3. One side of the first conductivity type semiconductor active layer 3 has a second conductivity type semiconductor body region 4, and the surface of the second conductivity type semiconductor body region 4 has an adjacent first conductivity type semiconductor source region 6 and a second conductivity type semiconductor body in contact Zone 5, the first conductivity type semiconductor source region 6 and the second conductivity type semiconductor body contact region 5 lead to a termination metallization source S on the surface; the other side of the first conductivity type semiconductor active layer 3 has a first conductivity type semiconductor drain Zone 7, the surface of the first conductivity type semiconductor dr...
Example Embodiment
[0028] Example 2
[0029] Figure 4b A schematic diagram of the structure of an extended-gate SOI LDMOS device with segmental change doping in the drift region is given. Compared with Example 1, the doping concentration of the drift region 3a in the device of this example increases stepwise from close to the body region 4 to close to the drain region 7. The segmentally doped drift region will weaken the influence of RESURF effect on the electric field distribution in the drift region in SOI devices. Therefore, compared with the device in Example 1, the withstand voltage of the device of this example is significantly improved, but since the drift region requires segmental doping, the process requirements are higher.
Example Embodiment
[0030] Example 3
[0031] Figure 4c A schematic diagram of the structure of an extended gate SOI LDMOS device doped with variable conductivity in the high resistance region is given. Compared with Embodiment 2, the device of this example adopts doping of the second conductivity type in the part of the high resistance region 10 of the extended gate close to the gate contact region 9, and adopts the doping of the first conductivity type in the part close to the field stop region 11. Doped. Adopting the doping of the first conductivity type in the part close to the field stop region 11 can avoid the drift region after the doping of the second conductivity type near the field stop region 11 is fully depleted in the high resistance region 10 when the device is turned off. The adverse effect of longitudinal electric field strength. Therefore, the withstand voltage of the device of this example is improved compared with the device of the second embodiment. However, because the doping...
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