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Routing adaptive asynchronous 2d-torus network-on-chip system and its design method

A 2d-torus, network-on-chip technology, applied in the transmission system, digital transmission system, data exchange network, etc., can solve the problems of not being able to dynamically adjust the routing direction according to the congestion state in real time, and waste routing resources.

Active Publication Date: 2017-05-24
NORTHEASTERN UNIV LIAONING
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  • Application Information

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Problems solved by technology

However, this type of algorithm is passive and blind. It can only distribute and transmit data packets in advance, and cannot dynamically adjust the routing direction according to the congestion status in real time.
Therefore, when the network is congested, routing resources may be wasted, and the efficiency of data transmission will be reduced, which will eventually lead to a rapid decline in routing performance.

Method used

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  • Routing adaptive asynchronous 2d-torus network-on-chip system and its design method
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  • Routing adaptive asynchronous 2d-torus network-on-chip system and its design method

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Embodiment Construction

[0057] The specific implementation of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0058] The route-adaptive asynchronous 2D-Torus network-on-chip of this embodiment adopts a 4×4 structure, such as figure 1 As shown, it includes: 16 asynchronous routing nodes and 16 IP cores, of which 16 asynchronous routing nodes, according to the 2D-Torus topology structure, adopts the asynchronous handshake communication mechanism to form a 4×4 asynchronous 2D-Torus network on chip. One IP core is mounted on each asynchronous routing node; the asynchronous routing node is used to send data from the corresponding output port to the adjacent node according to the information carried in the data, until the current asynchronous routing node is the destination address asynchronous routing node;

[0059] The asynchronous routing node in this embodiment, such as figure 2 As shown, the asynchronous routing node has five ports including ...

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Abstract

A routing adaptive asynchronous 2D-Torus network on chip and its design method, a plurality of asynchronous routing nodes construct the network-on-chip according to the 2D-Torus topology and asynchronous handshake communication mechanism; each asynchronous routing node has east, west, south, The northbound port and the local port have five ports in total, and each port includes an input terminal, a data receiving module, a data decoding module, a routing calculation module, a crossbar switch module, a data arbitration module, a data encoding module, a data sending module and an output terminal; the method Including: design the interface behavior of each port of the asynchronous routing node, and describe the data flow inside the asynchronous routing node; design the data structure of the data transmission in the asynchronous network on chip; design the port in the asynchronous finite state machine method module; complete the hardware programming of each module; construct an asynchronous routing node; construct an N×N asynchronous 2D‑Torus network on chip.

Description

technical field [0001] The invention belongs to the field of asynchronous circuit design, and in particular relates to a route-adaptive asynchronous 2D-Torus (two-dimensional ring) on-chip network and a design method thereof. Background technique [0002] With the rapid development of integrated circuit technology, the scale of the system is getting larger and larger, and the clock frequency is getting higher and higher. Problems with traditional bus clocking and power consumption are becoming more and more difficult to solve. A network on chip (Network on Chip, NoC) can solve these problems very well, and has gradually become a standard communication architecture for multi-core on a chip. At present, most networks on a chip adopt a synchronous communication mechanism, and the communication between network nodes is driven by a single clock. Only a small number of on-chip networks use asynchronous communication mechanisms, and the communication between network nodes is cont...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/741H04L12/771H04L12/865H04L45/74H04L45/60H04L47/6275
Inventor 李贞妮李晶皎方志强
Owner NORTHEASTERN UNIV LIAONING
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