Micro-electromechanical systems (MEMS) device assembling technology

Abstract

The invention relates to a micro-electromechanical systems (MEMS) device assembling technology and relates to the field of semiconductor device manufacture. The MEMS device assembling technology realizes connection of a MEMS chip and other semiconductor chips by direct bonding of the MEMS chip and the other semiconductor chips, utilizes a through-silicon-vias technology to prepare interconnection lines thereby realizing connection of a bonding chip and an external device and reducing connection lines connecting the chips, reduces device failure probability, saves a device packaging volume, reduces device power consumption, improves bonding chip heat conditions, effectively improves device performances and greatly improves a product yield rate.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing, in particular to a MEMS device integration process. Background technique [0002] At present, as the application fields of MEMS (Micro-electromechanical Systems, micro-electromechanical systems) chips become more and more extensive, it is necessary to integrate and package MEMS chips with other semiconductor chips; and in order to save the packaging area of ​​the overall device structure, usually The stacking method sets the MEMS chip on top of other chips. [0003] figure 1 It is a structural schematic diagram of a traditional MEMS chip integrated package; such as figure 1 As shown, in the traditional MEMS chip integration process, in order to reduce the overall packaging area, the chip a is first stacked on the chip b, and after the interconnection between the chip a and the chip b is realized through the wire 11, Then carry out the final packaging process; because the incre...

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Problems solved by technology

[0003] figure 1 It is a structural schematic diagram of a traditional MEMS chip integrated package; such as figure 1 As shown, in the traditional MEMS chip integration process, in order to reduce the overall packaging area, the chip a is first stacked on the chip b, and after the interconnection between the chip a and the chip b is realized through the wire 11, Then carry out the final packaging process; because the increased lead 111 will bring defects such as heat generation and increased power consumption, and when performing the bonding process, the lead 11 will also be adversely affected by various factors such as the process and the environment, and may even cause The failure of the device, thereby reducing the performance and yield of the prepared device product

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