Method for interconnecting back faces of wafer level chips during packaging

Abstract

The invention discloses a method for interconnecting back faces of wafer level chips during packaging. Blocking materials on a wafer welding cushion are removed through laser etching, a certain area of surface of the welding cushion is exposed to be connected with a metal wiring layer, and electricity of an element area is led to the back faces of wafers. Through the method that the blocking materials on the welding cushion are removed directly through laser etching, the process steps of photoresist coating, photo-etching exposure, developing, photoresist removing and the like are omitted; by selecting an appropriate laser wavelength, adjusting the laser focusing position, adjusting the energy, focus spot area, acting pulse number and other parameters of lasers acting at the bottom of a first opening and controlling laser etching to reach the surface of the welding cushion without penetrating through the welding cushion, a large area of the welding cushion is exposed. The method is convenient to operate, the contact area of the welding cushion and the metal wiring layer is enlarged, and conductivity is more reliable.

Description

Technical field [0001] The present invention relates to a method for wafer-level chip packaging, in particular to a method for forming openings for exposing solder pads in wafer-level chip packaging to realize backside interconnection. Background technique [0002] Such as figure 1 As shown, the general structure of the wafer includes several chip units. Each chip unit includes a substrate 1 and a dielectric layer 4 on the front surface of the substrate. The front surface of the substrate is provided with a component area 8, and the periphery of the component area is provided with several The soldering pad 2 is located in the dielectric layer, and the component area is electrically connected to the surrounding soldering pads; in this structure, the soldering pad and the substrate are separated by dielectric material. At present, the TSV packaging steps of wafer-level chips include making an opening on the back of the wafer substrate, which extends from the back of the wafer to th...

AI Technical Summary

Problems solved by technology

Removing the barrier material on the pad usually adopts etching method or laser drilling or mechanical cutting, however, using the etching method must mask, which increases the photolithography process; using laser drilling (such as figure 2 When the opening through the pad is formed by mechanical cutting, the opening can only expose the side of the pad, the area that can be connected to the circuit is small, the electrical conduction performance is not reliable enough, and the structural strength between the pad and the metal circuit is also relatively weak. weak

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