Integrated method of surface channel CMOS (complementary metal oxide semiconductor) logic device and SONOS (silicon-oxide-nitride-oxide-silicon) device

Abstract

The invention discloses an integrated method of a surface channel CMOS (complementary metal oxide semiconductor) logic device and an SONOS (silicon-oxide-nitride-oxide-silicon) device. The method comprises steps as follows: a gate oxide layer, an ONO layer and a polycrystalline silicon layer are formed; a gate polycrystalline silicon layer of the SONOS device is subjected to N type ion implantation; a fourth silicon nitride film is grown; a photoresist pattern of a first part of a first polysilicon gate is defined; the fourth silicon nitride film is etched; photoresist patterns of a second part of the first polysilicon gate and a polysilicon gate of the CMOS device are defined; polysilicon gates of the devices are formed while the polycrystalline silicon layer is etched; LDD (lightly doped drain) injection is performed; side walls are formed; source drain injection is performed; polysilicon gate doping of the CMOS logic device is realized while the source drain injection is performed; PSG (phosphosilicate glass) is grown and flattened; USG (undoped silicon glass) is grown; and contact holes are formed. With the adoption of the integrated method, a thermal process of boron penetration of a PMOS (P-channel metal oxide semiconductor) device can be reduced, the number of photoetching models is reduced, and a small-size surface channel device and a high-density storage device can be integrated.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to an integration method of a surface channel CMOS logic device and a SONOS (silicon / silicon dioxide / silicon nitride / silicon dioxide / silicon) device. Background technique [0002] In the small-sized surface channel process, it is necessary to take into account the application of the high-end logic process, that is, the integration of the surface channel CMOS logic device process and the SONOS process. [0003] In surface channel CMOS logic devices, both NMOS devices and PMOS devices are surface channels. The surface channel requires the polysilicon gate of the NMOS device to be N-type doped, while the polysilicon gate of the PMOS device is P-type doped. Therefore, for surface channel CMOS logic devices, the doping of polysilicon gates of NMOS devices and PMOS devices should be carried out separately. Generally, the polysilicon gates of surface channe...

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Problems solved by technology

When the device size is further reduced to 90 nanometers, or even 65 nanometers, the thickness of the gate oxide layer is further reduced, which cannot resist the boron in the polysilicon penetrating into the channel through the gate oxide layer, causing serious leakage of the device

[0006] As can be seen from the above, since the boron implantation of the polysilicon gate of the surface channel PMOS device in the existing method must be placed before the hard mask layer of the polysilicon gate is formed, the existing method cannot avoid the boron implantation of the polysilicon gate of the surface channel PMOS device. The problem of boron diffusion into the channel during the subsequent thermal process, when the size of the device is further reduced, the integration of surface channel CMOS logic devices and SONOS devices cannot be realized

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