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A method of manufacturing a semiconductor planarization layer

A planarization layer and manufacturing method technology, which is applied in semiconductor/solid-state device manufacturing, photoplate process of patterned surface, optics, etc., can solve insufficient solvent precipitation, large thickness of planarization layer, surface hardening of planarization layer, etc. problem, to achieve the effect of improving reliability, optimizing taper angle and ensuring consistency

Active Publication Date: 2017-09-01
EVERDISPLAY OPTRONICS (SHANGHAI) CO LTD
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  • Abstract
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  • Claims
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Problems solved by technology

[0010] In order to overcome the above-mentioned problems in the past, the inventors have found through repeated research that the fundamental reason for the insufficient solvent precipitation in the planarization layer is that the thickness of the planarization layer is too large, and the surface hardening of the planarization layer is easily caused during the baking process. , to prevent subsequent solvent precipitation

Method used

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  • A method of manufacturing a semiconductor planarization layer
  • A method of manufacturing a semiconductor planarization layer
  • A method of manufacturing a semiconductor planarization layer

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0037] figure 1 It is a flow chart showing the process of completing the planarization layer by applying glue twice in Embodiment 1 of the present invention. In the manufacturing method of the semiconductor planarization layer described in this embodiment, the glue coating operation of the planarization layer is implemented twice, and the thickness of each glue coating is set to 1.5 μm. The manufacturing method includes the following steps implemented in sequence:

[0038] The first coating, baking and drying step S211: coating the photoresist used to form the first planarization layer on the lower layer film with a thickness of 1.5 μm, and softening the first planarization layer after coating Baking treatment, and further using a vacuum drying device to implement low-temperature drying treatment to remove the solvent in the first planarization layer;

[0039] The first exposure and development step S221: performing exposure treatment and development treatment on the first p...

Embodiment 2

[0047] figure 2 It is a flow chart showing the three times of gluing to complete the planarization layer in Embodiment 2 of the present invention. In the manufacturing method of the semiconductor planarization layer in this embodiment, the glue coating operation of the planarization layer is implemented three times, and the thickness of each glue coating is set to 1 μm. The manufacturing method includes the following steps implemented in sequence:

[0048] The first coating, baking and drying step S311: Coating the photoresist for forming the first planarization layer on the lower layer film with a thickness of 1 μm, and performing soft baking on the first planarization layer after coating treatment, and further use a vacuum drying device to implement low-temperature drying treatment to remove the solvent in the first planarization layer;

[0049] First exposure and development step S321: performing exposure treatment and development treatment on the first planarization laye...

Embodiment 3

[0059] Except not carrying out all deslagging and ashing steps, it carried out similarly to Example 1, and obtained the final planarization layer. As a result, the solvent precipitation rate of the photoresist in the finally formed planarization layer can reach about 93%, the total film thickness uniformity of the finally formed planarization layer can reach about 8-15%, and the taper of the planarization layer The angle can reach about 40-60°.

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Abstract

The invention provides a manufacturing method of a semiconductor planarization layer. The manufacturing method comprises the following steps: a coating, baking and drying step, that is, a photoresist for forming a planarization layer is coated on a lower layer film and then the baking treatment and drying treatment are performed; an exposure and development step, that is, the exposure treatment and the development treatment are performed on the planarization layer after the coating, baking and drying step; the manufacturing method is characterized in that the coating, baking and drying step is carried out in at least twice according to the required coating thickness of the planarization layer to be manufactured; the exposure and development step is carried out for at least once. The manufacturing method can improve the taper angle of the planarization layer, reduce the undercut phenomenon of the planarization layer, and prevent the breakage of an upper layer film of the planarization layer, so as to improve the reliability of products.

Description

technical field [0001] The invention belongs to the manufacturing process of semiconductor integrated circuits in the field of flat panel display technology, and in particular relates to a method for manufacturing a semiconductor planarization layer. Background technique [0002] In recent years, in the field of flat panel display technology, for example, in the manufacturing process of thin film transistors (TFTs), a planarization layer (PLN: Planarization layer) has been widely used. The use of the planarization layer can smooth the in-plane level difference caused by various layer patterns on the substrate of the display device. The advantage of using the planarization layer is that it can reduce the area of ​​the black matrix, increase the aperture ratio of the panel, increase the light transmittance, and reduce the power consumption of the product. [0003] However, the following problems arise in the conventional production process of the planarization layer. Due to ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/312G03F7/00
CPCG03F7/00H01L21/3105H01L21/31058
Inventor 高印柯其勇颜圣佑陈智冈
Owner EVERDISPLAY OPTRONICS (SHANGHAI) CO LTD
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