Gallium nitride based field effect transistor and preparation method thereof
A gallium nitride base field and transistor technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as poor Schottky contact, insufficient component stability, and poor thermal stability. Achieve good thermal conductivity and thermal stability, reduce spontaneous thermal effects, and reduce current collapse effects
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Embodiment 1
[0037] refer to figure 1 , the transistor 100 of this embodiment is stacked with a substrate 101, a buffer layer 102, a gallium nitride layer 103 and an aluminum gallium nitride layer 104 sequentially from bottom to top, and the upper surface of the aluminum gallium nitride layer 104 is provided with a source electrode 105, The drain 106 and the insulating layer 107 between them, the gate 108 is disposed on the insulating layer 107 , and the metal electrode layer 109 is disposed on the top of the gate 108 . A passivation layer 110 is covered on the above structure, and the passivation layer 110 is respectively provided with openings above the source electrode 105, the drain electrode 106 and the metal electrode layer 109, and thickened electrodes 111a, 111b and 111c are respectively provided in the openings .
[0038] The insulating layer 107 can be an oxide, such as Gd 2 o 3 、Pr 2 o 3 , La 2 o 3 , HfO 2 , ZrO 2 、Al 2 o 3 , Y 2 o 3 、Sc 2 o 3 、Er 2 o 3 、 Ta 2 ...
Embodiment 2
[0053] refer to figure 2 , the transistor 200 of this embodiment has a substrate 201, a buffer layer 202, a gallium nitride layer 203, and an aluminum gallium nitride layer 204 stacked sequentially from bottom to top, and the upper surface of the aluminum gallium nitride layer 204 is provided with a source electrode 205 and The drain 206 and the insulating layer 207 therebetween. A portion of the upper surface of the AlGaN layer 204 is recessed to form a groove 2041 , and the insulating layer 207 is also recessed accordingly. A gate 208 made of conductive diamond-like carbon is disposed on the insulating layer 107 corresponding to the groove 2041 , and a metal electrode layer 209 is disposed on the top of the gate 208 . The passivation layer 210 is covered on the above structure, and the passivation layer 210 is respectively provided with openings above the source electrode 205, the drain electrode 206 and the metal electrode layer 209, and thickened electrodes 211a, 211b an...
Embodiment 3
[0062] refer to image 3 , the transistor 300 of this embodiment is stacked with a substrate 301, a buffer layer 302, a gallium nitride layer 303 and an aluminum gallium nitride layer 304 sequentially from bottom to top, and the upper surface of the aluminum gallium nitride layer 304 is provided with a source electrode 305, The drain 306 and the gate 308 located between them, the top of the gate 308 is provided with a metal electrode layer 309 . A passivation layer 310 is covered on the above structure, and the passivation layer 310 is respectively provided with openings above the source electrode 305, the drain electrode 306 and the metal electrode layer 309, and thickened electrodes 311a, 311b and 311c are respectively provided in the openings. .
[0063] The gate 308 is a p-type doped conductive DLC, and the pure DLC is doped with less than 5wt% of boron (B), aluminum (Al), indium (In) or a combination thereof. The materials of other components are the same as in Embodime...
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