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Formation method of semiconductor structure

A technology of semiconductor and gate structure, applied in the field of semiconductor structure formation, can solve the problems of unstable leakage current performance, non-uniformity, poor feature size of fin surface morphology, etc., to achieve the effect of accurate and uniform structure size and avoid damage

Active Publication Date: 2018-06-29
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology

[0005] However, in the existing fin field effect transistors, the surface morphology of the fins is poor, and the feature size (CD, Critical Dimension) is not uniform, which makes the fin field effect transistors prone to leakage current and unstable performance.

Method used

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Embodiment Construction

[0034] As mentioned in the background, in the existing fin field effect transistors, the surface morphology of the fin portion is poor, and the feature size is not uniform.

[0035] After research, it is found that in a process embodiment of forming a fin field effect transistor, such as figure 1 As shown, before the gate structure 103 is formed on the surface of the dielectric layer 102 and the top and sidewall surfaces of the fin 101, it is necessary to use an ion implantation process to dope P-type or N-type ions in the fin 101, so that the fin Portion 101 becomes an active region. In order to protect the fin 101 from damage during the ion implantation process, before the ion implantation process, a pad oxide layer 110 (such as figure 2 shown).

[0036]The thermal oxidation process is carried out in a high-temperature oxygen atmosphere, and by diffusing oxygen into the exposed sidewalls and top surfaces of the fins, the oxygen is combined with the semiconductor material ...

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Abstract

A method for forming a semiconductor structure, comprising: providing a substrate with fins on the surface, a dielectric layer on the surface of the substrate and part of the sidewall surfaces of the fins, the surface of the dielectric layer is lower than the top surface of the fins; A first protective layer is formed on the surface of the layer, the sidewall and the bottom surface of the fin, and the density of the first protective layer is greater than that of silicon oxide; an oxidation process is used to form a second protective layer on the surface of the first protective layer; on the surface of the second protective layer Forming a mask layer, the mask layer exposes part of the second protective layer on the surface of the fin portion, and the second protective layer is used to isolate the first protective layer and the mask layer; using the mask layer as a mask, ion implantation process is used on the fin Ion doping inside the part; after the ion implantation process, the mask layer, the second protection layer and the first protection layer are removed, and the surface of the dielectric layer, and part of the sidewall and bottom surface of the fin are exposed. The formed semiconductor structure has good morphology and precise and uniform feature size.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. As the most basic semiconductor device, transistors are currently being widely used. Therefore, with the increase of component density and integration of semiconductor devices, the gate size of planar transistors is getting shorter and shorter. The ability of traditional planar transistors to control channel current Weakened, resulting in short channel effect, resulting in leakage current, and ultimately affecting the electrical performance of semiconductor devices. [0003] In order to overcome the short-channel effect of the transistor and suppress the leakage current, a Fin Field Effect Transistor (Fin FET) is proposed i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/78
Inventor 赵海
Owner SEMICON MFG INT (SHANGHAI) CORP
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