Preparation method of silicon germanium epitaxial layer in cmos device technology

Abstract

The invention provides a preparation method of a germanium-silicon epitaxial layer for CMOS device processing. The preparation method comprises the steps: forming a first hard mask layer and a second hard mask layer on a semiconductor device substrate; removing the second hard mask layer in a PMOS area to expose the PMOS area; and implanting ions in a source-drain area of the PMOS and then etching the surface of the source-drain area and performing germanium-silicon epitaxial growth. As plasmas damages the surface of the source-drain area of the PMOS, the etching rate of the surface of the following etching source-drain area is improved and the etching time on the surface of the source-drain area is reduced correspondingly. Therefore, the damage to the surface of the isolation structure of a shallow trench is reduced during the etching process to avoid exposure of the surface of an active area of the PMOS because the surface of the isolation structure of the shallow trench is damaged seriously so as to overcome the defect that redundant silicon epitaxial layers are grown at the edge of the PMOS in the prior art.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for preparing a silicon-germanium epitaxial layer in a CMOS device process. Background technique [0002] Traditional silicon technology is facing a series of new problems in the process of development according to Moore's law. The problems caused by the continuous shrinking of feature size and the reduction of gate dielectric layer thickness include parasitic effects, increased leakage current, serious short channel effect, thermal Carrier effects and mobility degradation, difficulty and cost of process technology, diffraction during lithography exposure, etc., make the performance of CMOS circuits largely restricted by PMOS. [0003] In 90nm PMOS, the source and drain of the device are usually removed by etching, and then the silicon germanium layer (SiGe) is redeposited, so that the source and drain will generate a compressive stress on the channel, thereby imp...

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Problems solved by technology

[0010] In the above process, especially in the 40nm and 28nm process, the growth and control of SiGe have presented huge challenges, especially the limitation of the process window. In the etching process in step L4, such as Figure 2d As shown, the oxide film on the surface of the shallow trench isolation structure 108 will be etched, and the boundary surface of the PMOS active region 101 will be exposed, and the cleaning process after the SiGe etching and before the SiGe growth will cause the shallow trench isolation The further loss of the oxide layer (Oxide) on the structure (STI) causes the gate (Poly) to fail to completely cover the boundary of the PMOS active area in the SRAM area, and the edge of the PMOS active area is exposed during SiGe epitaxial growth and grows redundant SiGe epitaxy 107, forming defects such as Figure 2e As shown, and the size and growth direction of these SiGe residues cannot be controlled, which will seriously affect the subsequent process and even lead to SRAM failure. Therefore, it is particularly important to find a suitable process to prevent the growth of SiGe residues on the edge of the PMOS active region. , thereby addressing the greatest process challenges in 45 / 40nm integrated circuits

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