Method for forming fin field-effect transistors, and method for forming MOS transistors

Abstract

The invention provides a method for forming fin field-effect transistors, and a method for forming MOS transistors. The method for forming fin field-effect transistors comprises the steps of providing a semiconductor substrate provided with a plurality of discrete fin parts; forming a pseudo grid crossing the sidewalls of the fin parts and the top surfaces of the fin parts; forming a dielectric layer covering the pseudo grid and the semiconductor substrate, wherein the surface of the dielectric layer is higher than the top surface of the pseudo grid; implanting first ions and implanting cured ions in the dielectric layer to increase the density of the dielectric layer; planarizing the dielectric layer to expose the surface of the pseudo grid; removing the pseudo grid to form a groove, and forming a metal gate in the groove. According to the invention, the defect of recesses is prevented from occurring in the dielectric layer.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a fin field effect transistor and a method for forming a MOS transistor. Background technique [0002] With the continuous development of semiconductor process technology, the process node is gradually reduced, and the gate-last (gate-last) process has been widely used to obtain an ideal threshold voltage and improve device performance. However, when the feature size (CD, Critical Dimension) of the device is further reduced, even if the gate-last process is adopted, the structure of the conventional MOS field effect transistor can no longer meet the requirements for device performance, and the fin field effect transistor (FinFET) as a conventional device substitution has received extensive attention. [0003] figure 1 A schematic structural view of a fin field effect transistor in the prior art is shown. like figure 1 As shown, it includes: a se...

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Problems solved by technology

[0006] In the prior art, when the dielectric layer is planarized, recessed defects are easily generated in the dielectric layer, and metal residues are likely to be caused when the metal gate electrode is subsequently formed.

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