A kind of soi dual-port sram unit and its manufacturing method
A manufacturing method and dual-port technology, which are applied in the fields of electrical components, semiconductor/solid-state device manufacturing, digital memory information, etc., can solve the problems of SOI dual-port SRAM cells occupying a large area, weak anti-noise ability, poor stability, etc. Floating body effect, improving noise immunity, and facilitating the effect of fully custom SRAM chips
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Embodiment 1
[0088] The present invention provides a SOI dual-port SRAM unit, please refer to figure 1 , shown as a schematic diagram of the circuit principle of the SOI dual-port SRAM cell, including:
[0089] The first inverter 1 is composed of a first PMOS transistor 101 and a first NMOS transistor 102;
[0090] The second inverter 2 is composed of a second PMOS transistor 201 and a second NMOS transistor 202;
[0091] The acquisition transistor 3 is composed of a third NMOS transistor 301, a fourth NMOS transistor 302, a fifth NMOS transistor 303 and a sixth NMOS transistor 304; the source of the third NMOS transistor 301 is connected to the first inverter The output end and the input end of the second inverter, the gate is connected to the write word line WL1 of the memory, and the drain is connected to the write bit line BL1 of the memory; the source of the fourth NMOS transistor 302 is connected to the first The output end of the two inverters and the input end of the first invert...
Embodiment 2
[0103] The present invention also provides a method for making an SOI dual-port SRAM unit, comprising the steps of:
[0104] Step S1 is first performed: provide an SOI substrate including a back substrate, an insulating buried layer, and a top layer of silicon in sequence from bottom to top, and form a shallow trench isolation structure in the top layer of silicon to define an active region.
[0105] As an example, such as Figure 8 As shown, six active regions 20a, 20b, 20c, 20d, 20e and 20f are defined, wherein these six active regions 20e, 20a, 20b, 20c, 20d and 20f are arranged in parallel in sequence, and each active region is surrounded by a The shallow trench is filled with an insulating material to form a shallow trench isolation structure. In this embodiment, the insulating material is silicon dioxide.
[0106] Then execute step S2: as Figure 9 As shown, an N well 30, a first P well 40 and a second P well 50 are fabricated in the top silicon according to the posit...
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