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Packages with multiple I/O side solderable terminals

A terminal and frame technology, applied in the field of leadless packaged semiconductor devices and their manufacture

Active Publication Date: 2018-11-23
NEXPERIA BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It is known that leadless packaged semiconductor devices have advantages over leaded packages

Method used

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  • Packages with multiple I/O side solderable terminals
  • Packages with multiple I/O side solderable terminals
  • Packages with multiple I/O side solderable terminals

Examples

Experimental program
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Embodiment Construction

[0019] The present invention is known for addressing challenges in packaging semiconductor devices for use in portable systems. It is known that leadless packaged semiconductor devices offer advantages over leaded packages. These advantages include better electrical performance due to reduced lead inductance, good heat dissipation through the use of exposed thermal pads to improve heat conduction to the PCB (printed circuit board), reduced package thickness, and smaller Footprint, which reduces the area occupied on the PCB. Examples of leadless packaged semiconductor devices include QFN (Quad Flat No-lead Device) and DFN (Discrete Flat No-lead device). However, a disadvantage of leadless packaged semiconductor devices is that it is difficult to inspect solder joints when mounted on a PCB. Conventional inspection techniques use a system called automated optical inspection (AOI) in which cameras scan leadless packages mounted on PCBs for various defects such as open connection...

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Abstract

According to an exemplary embodiment, there is provided a leadless packaged semiconductor device having top and bottom opposing major surfaces and sidewalls extending therebetween. The leadless packaged semiconductor device includes a leadframe subassembly having an array of two or more leadframe sections with a semiconductor die disposed on each leadframe section. There are at least five I / O terminals, wherein each of the I / O terminals includes a respective metal side pad; and the respective metal side pad is disposed in the recess. This embodiment is characterized in that each side pad is plated. The plated side pads accept solder, and the recesses include a half-moon of solder.

Description

technical field [0001] The present disclosure relates to integrated circuit (IC) packaging. In particular, the present disclosure relates to leadless packaged semiconductor devices and methods of manufacturing the same. Background technique [0002] The electronics industry has always relied on advances in semiconductor technology to enable higher performance devices in more compact areas. In many applications, achieving higher performance devices requires integrating a large number of electronic devices on a single silicon wafer. As the number of devices in a given area of ​​a silicon wafer increases, the fabrication process becomes more difficult. [0003] A wide variety of semiconductor devices have been manufactured, which have various applications in many disciplines. These silicon-based semiconductor devices generally include metal-oxide-semiconductor field effect transistors (MOSFETs), such as p-channel MOS (PMOS), n-channel (NMOS) and complementary MOS (CMOS) tran...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/495
CPCH01L23/4952H01L23/49537H01L21/561H01L23/3107H01L23/49562H01L23/49575H01L2924/0002H01L2924/00
Inventor 梁志豪贺伟鸿森克·哈贝尼希特波姆皮奥·乌马里何伟强冯而威
Owner NEXPERIA BV