Full-period or half-period synchronous frequency measurement and correction digital demodulation detection system and detection method of amplitude modulation signal

Abstract

The invention relates to a full-cycle or half-cycle synchronous frequency measurement corrected digital demodulation detection system and detection method of amplitude-modulated signals. The full-cycle or half-cycle synchronous frequency measurement corrected digital demodulation detection system and method can be adopted to realize the amplitude detection of the amplitude-modulated signals. According to the detection system, a micro controller unit is adopted to control a high-speed analog-to-digital conversion unit to perform signal acquisition, and lock-in amplified digital integral and filtering can be realized through absolute value cumulative averaging calculation; and the starting point of a full cycle or a half cycle is captured, and the frequency of the signals is measured through using high-frequency counting, and frequency correction is performed on a detection result. Compared with an existing detection system using a lock-in amplifying circuit, the detection system of the invention has the advantages of simple circuits, no middle debugging process and high detecting precision; compared with an existing simplified digital demodulation detection system, the detection system of the invention can assist in decreasing system detection noise and improving detection accuracy under the premise that the complexity of the circuits and algorithms as well as detection time and cost are not increased.

Description

technical field [0001] The invention relates to a frequency error compensation correction technology for digital demodulation of an amplitude modulation signal detection system, in particular to a digital demodulation method for a signal detection system of a raster scanning spectrometer. Background technique [0002] For the demodulation of the amplitude modulation detection signal, the detection system is usually implemented by a lock-in amplifier circuit: the detection signal and the reference signal (a square wave signal with the same frequency and phase as the measured signal) are subjected to phase-sensitive detection, low-pass filtering, and amplification to obtain The amplitude signal of the same frequency component as the modulating signal, thus effectively suppressing noise and harmonics. Its circuit includes band-pass filtering and amplification of the detection signal, phase shifting of the reference signal, phase-sensitive detection, low-pass filtering and other...

AI Technical Summary

Problems solved by technology

[0005] CN102916665A discloses a "two-phase digital lock-in amplifier and its digital domain genlock algorithm", which realizes automatic tracking filtering and genlock functions, and can adapt to input signals with frequency changes, but requires two phases as reference signals The square wave signal with a difference of 90° has the same frequency as the detection signal, and it is necessary to collect three signals and send them to the PC. The phase-locking algorithm is implemented by the PC, which cannot meet the requirements of spectral scanning for real-time sampling.

However, due to the frequency fluctuation of the detection signal itself and the limitation of ADC sampling frequency, it will cause the selection error of the last sampling point of each signal cycle. Although the average of multiple cycles is taken, the measurement results of the detection signal still have random errors, which are manifested as Noise in test results

[0011] It can be seen that the existing digital lock-in amplifiers have detection noise problems for detection signals with unstable frequencies.

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