Method of manufacturing a semiconductor device

Abstract

A material layer is formed over a substrate. A negative tone photoresist layer is formed over the material layer. An exposure process is performed to the negative tone photoresist layer. A post-exposure bake (PEB) process is performed to the negative tone photoresist layer. After the exposure process and the PEB process, the negative tone photoresist layer is treated with a solvent. The solvent contains a chemical having a greater dipole moment than n-butyl acetate (n-BA).

Description

technical field [0001] The present invention relates to a method of manufacturing a semiconductor device. Background technique [0002] The semiconductor integrated circuit (integrated circuit, IC) industry has experienced rapid growth. Technological advances in integrated circuit materials and design have resulted in generations of integrated circuits where each generation has smaller and more complex circuits than previous generations. However, these advances have increased the complexity of processing and manufacturing integrated circuits, and for these advances to be realized, similar developments are required in integrated circuit processing and manufacturing. In the course of integrated circuit development, functional density (i.e., the number of interconnected devices per wafer area) has broadly increased, while geometry size (i.e., the number of devices that can be The smallest member (or line) that is generated) has been reduced. [0003] As the size of semicondu...

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Problems solved by technology

However, even negative tone development processes may still have disadvantages regarding depth of focus (DOF), line width roughness (LWR) or scum

These problems reduce lithography efficacy and can lead to reduced yield or even device failure

[0004] Thus, although existing negative-tone developing processes have been widely used for their intended use, they are not entirely satisfactory in all respects.

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