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Longitudinal super-junction enhanced MIS HEMT device

An enhanced, vertical technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of large gate-to-drain spacing, increased on-resistance, early breakdown of devices, etc., and achieve high off-state breakdown voltage, conduction Effect of resistance reduction

Inactive Publication Date: 2016-10-26
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, lateral GaN HEMTs have the following disadvantages: 1. In the off state, it is easy to form a peak electric field on the side of the gate close to the drain terminal, which leads to early breakdown of the device and limits the improvement of the withstand voltage; 2. There is a buffer layer leakage current in the off state, and excessive A large buffer layer leakage current will lead to early breakdown of the device, which limits the application of GaN HEMTs in high voltage; 3. The lateral GaN HEMT device mainly withstands the withstand voltage through the active region between the gate and the drain, so the high-voltage GaN HEMT Larger gate-to-drain spacing is required, causing the device to occupy an excessively large chip area, which is not conducive to the development trend of miniaturization
[0005] For conventional vertical GaN HEMTs, vertical devices cannot fully use 2DEG to achieve conduction, and the conduction current needs to flow through the buffer layer, which makes the on-resistance much higher than that of lateral devices; and with the increase of breakdown voltage, it needs to be reduced The doping concentration of the buffer layer increases its thickness, which makes the on-resistance increase sharply and restricts the forward current capability of the device. Therefore, conventional vertical GaN HEMT devices have a contradictory relationship between breakdown voltage and on-resistance

Method used

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Examples

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Embodiment 1

[0030] image 3 A schematic diagram of the whole cell structure of a longitudinal superjunction enhanced MIS HEMT device is shown. The device of this example includes a drain electrode 1, a substrate 2, a buffer layer 3, a barrier layer 4, a channel layer 5, and a barrier layer 6 that are sequentially stacked from bottom to top. electrode 7; the middle part of the barrier layer 6 is provided with an insulating gate structure; the upper surface of the barrier layer 6 between the source electrode 7 and the insulating gate structure has a dielectric passivation layer 10; it is characterized in that the lining The bottom 2 and the channel layer 5 are N-type doped, and the barrier layer 4 is P-type doped; the insulating gate structure extends downwards in the vertical direction, passing through the barrier layer 6, the channel layer 5 and the The barrier layer 4 extends into the buffer layer 3; the insulated gate structure is composed of an insulating gate dielectric 8 and a gate ...

Embodiment 2

[0033] Compared with Example 1, the lateral width of the insulated gate structure of the device in this example gradually increases from bottom to top, and other structures are the same as in Example 1, such as Figure 4 shown. The lateral width of the insulated gate structure gradually increases from bottom to top, which can effectively alleviate the curvature effect, avoid the early breakdown of the device caused by the concentration of the electric field, and increase the breakdown voltage of the device.

Embodiment 3

[0035] Compared with Example 1, the thickness of the insulating gate dielectric 8 vertically extending downwards of the device in this example gradually increases from top to bottom, and other structures are the same as in Example 1, such as Figure 5 shown. Gradually increasing the thickness of the insulating gate dielectric from top to bottom can effectively reduce the gate capacitance and improve the dynamic performance of the device, but the accumulation effect of the gate will be weakened.

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Abstract

The invention belongs to the semiconductor technology field and relates to a longitudinal super-junction enhanced MIS HEMT device. In the invention, a super-junction buffer layer, an N-type semiconductor buffer layer and a P-type semiconductor buffer layer are mutually compensated and exhausted so as to reach charge balance and increase dosage concentration. During positive conducting, because the dosage concentration of the super-junction buffer layer is high, a conduction resistance of the device is obviously reduced. Under a reverse blocking state, longitudinal electric fields in the buffer layer are uniformly distributed so as to realize a high off-state breakdown voltage. Simultaneously, a p-type doped barrier layer which is contacted with a groove grid sidewall is used to pinch off a vertical conductive channel of 2DEG and the buffer layer; and a voltage on an insulated grid electrode is used to control the conductive channel so as to realize an enhanced type. A device manufacturing technology in the invention is compatible with a traditional technology.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a vertical superjunction enhanced MIS HEMT (High Electron Mobility Transistor, high electron mobility transistor) device. Background technique [0002] High electron mobility transistors (HEMTs) based on GaN materials, due to high electron saturation velocity, high density two-dimensional electron gas (2DEG) and high critical breakdown electric field, make it in high current, low power consumption, high frequency and high voltage The switch application field has a huge application prospect. [0003] Lateral GaN HEMTs are favored in high-frequency and low-power applications due to their high-density two-dimensional electron gas (2DEG). The basic structure of the device is as follows: figure 1 shown. However, lateral GaN HEMTs have the following disadvantages: 1. In the off state, it is easy to form a peak electric field on the side of the gate close to the dra...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L29/20H01L29/778
CPCH01L29/0634H01L29/2003H01L29/7787
Inventor 罗小蓉彭富杨超吴俊峰魏杰邓思宇张波李肇基
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA