Semiconductor structure and formation method thereof

Abstract

The invention provides a semiconductor structure and a formation method thereof. The formation method of the semiconductor structure is that a semiconductor substrate is provided, the semiconductor substrate comprises a first region, a first fin part is formed on the first region, and an isolation layer is also formed on the semiconductor substrate; a first gate electrode structure crossing the first fin part is formed on the isolation layer; a first source-drain region is formed in the first fin part of the two sides of the first gate electrode structure; a dielectric layer is formed on the semiconductor substrate, and the dielectric layer covers the semiconductor substrate, the first fin part, the first gate electrode structure and the first source-drain region; the dielectric layer on the first region is etched so that a first contact hole arranged on the surface of the first source-drain region is formed; a first semiconductor epitaxial layer is formed on the surface of the first source-drain region, and the first type of doping ions are enabled to be doped in the first semiconductor epitaxial layer by using an in-situ doping technology; a metal silicide layer is formed on the surface of the first semiconductor epitaxial layer; and a metal plug fully filling the first contact hole is formed. According to the method, parasitic resistance of the formed semiconductor structure can be reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the continuous development of semiconductor process technology, process nodes are gradually reduced, and gate-last (gate-last) process has been widely used to obtain an ideal threshold voltage and improve device performance. However, when the feature size of the device is further reduced, even if the gate-last process is adopted, the structure of the conventional MOS field effect transistor can no longer meet the requirements for device performance, and the fin field effect transistor (Fin FET) is obtained as a multi-gate device. received widespread attention. [0003] For fin field effect transistors, as the size of the transistor continues to shrink, the parasitic resistance of the source and drain of the transistor has a more significant impact on the performance of the transisto...

AI Technical Summary

Problems solved by technology

[0005] In the prior art, ion doping is usually performed on the source and drain electrodes of FinFETs by source-drain ion implantation, but since ion implantation is likely to cause lattice damage, annealing is required after ion implantation to activate the dopant ions At the same time, lattice damage is repaired. During the annealing process, dopant ions are prone to diffuse, which reduces the concentration of dopant ions in the source and drain electrodes; and, after forming the source and drain electrodes, it is necessary to form a dielectric layer on the surface of the transistor, and then etch Etching the dielectric layer to form a contact hole on the surface of the source and drain, and then forming a metal silicide on the surface of the source and drain, the process of etching the dielectric layer to form a contact hole is also easy to cause damage to the surface of the source and drain, so that the source Dopant ion loss in the drain

Therefore, it is difficult to increase the concentration of dopant ions in the source and drain electrodes in the prior art, so that the performance of the fin field effect transistor formed by the prior art needs to be further reduced.

Images