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Preparing method of high K interface layer

A technology of interface layer and transition layer, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as high interface state and affect device performance, and achieve the goal of reducing interface state density, improving device performance, and improving properties Effect

Active Publication Date: 2017-01-11
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Application Information

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Problems solved by technology

[0009] However, the high-K interface layer grown by the thermal oxidation method is not easy to form a Hf-Si-O mixed structure with the high-k hafnium-based gate dielectric material, so that the interface state between the two is very high, which affects the performance of the device

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  • Preparing method of high K interface layer
  • Preparing method of high K interface layer
  • Preparing method of high K interface layer

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Embodiment Construction

[0039] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

[0040] Figure 1 to Figure 4 Each step of the method for preparing a high-K interface layer according to a preferred embodiment of the present invention is schematically shown.

[0041] Specifically, such as Figure 1 to Figure 4 As shown, the preparation method of the high-K interface layer according to the preferred embodiment of the present invention comprises:

[0042] The first step: providing a silicon substrate 100, and using H 2 SO 4 and H 2 o 2 mixed solution to clean the silicon substrate 100 to remove organic matter on the surface of the sample, such as figure 1 shown;

[0043] The second step: cleaning the Si substrate by RCA cleaning method;

[0044] The third step: cleaning the silicon substrate 100 with HF solution to effe...

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Abstract

The invention discloses a manufacturing method of a high K interface layer, comprising the following steps of 1, providing a silicon substrate, and cleaning the silicon substrate to remove organic matters on a sample surface by mixture solution of H2SO4 and H2O2; 2, cleaning the Si substrate by RCA; 3, cleaning the silicon substrate by HF (Hydrogen Fluoride) solution to effectively remove the original oxidation layer of the silicon substrate surface; 4, developing a SiO2 transition layer through chemical oxidization; 5, annealing under the atmosphere of pure deuterium gas and / or isotopes thereof to compact the SiO2 transition layer; and 6, depositing a high K material.

Description

technical field [0001] The present invention relates to the field of semiconductor manufacturing and the technical field of CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor), in particular to high-K gate dielectric / metal gate structure technology; more specifically, the present invention relates to the preparation of a high-K interface layer method. Background technique [0002] With the continuous development of large-scale integrated circuit technology, the feature size of metal-oxide-semiconductor field-effect transistors (MOSFETs), which are the core devices of silicon-based integrated circuits, has been continuously shrinking in accordance with Moore's law, and the gate dielectric layer must be reduced. thickness to maintain good performance by reducing the length of the gate. However, the thickness of the MOS tube gate dielectric is getting smaller and smaller, and it is close to its limit. So, to reduce gate leakage, a high diel...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/02H01L21/31
CPCH01L21/02043H01L21/02181H01L21/02214H01L21/02238H01L21/02255H01L21/31
Inventor 温振平
Owner SHANGHAI HUALI MICROELECTRONICS CORP