Method utilizing controllable defective graphene insertion layer to prepare metal-semiconductor alloy

A graphene and semiconductor technology, used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of poor quality and poor stability of the metal thin film layer, and achieve the effect of improving electrical performance, stable performance and reducing resistance

Active Publication Date: 2017-05-24
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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Problems solved by technology

[0004] In view of the above-mentioned shortcoming of prior art, the object of the present invention is to provide a kind of method that utilizes controllable defect graphene intercalation layer to prepare metal-semic

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  • Method utilizing controllable defective graphene insertion layer to prepare metal-semiconductor alloy
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  • Method utilizing controllable defective graphene insertion layer to prepare metal-semiconductor alloy

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[0031] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] see Figure 2 to Figure 8 It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic concept of the present invention, although only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the ...

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Abstract

The invention provides a method utilizing a controllable defective graphene insertion layer to prepare metal-semiconductor alloy. The method comprises steps that 1), a semiconductor substrate is provided; 2), graphene is formed don a surface of the semiconductor substrate; 3), ion injection into the graphene is carried out to acquire density-controllable defective graphene; 4), a metal layer is formed on the surface of the defective graphene; and 5), annealing processing for the structure acquired in the step 4) is carried out to form the metal-semiconductor alloy. Through forming the graphene insertion layer between the semiconductor substrate and the metal layer, contact characteristics of an interface of the semiconductor substrate and the metal-semiconductor alloy can be effectively improved, the metal-semiconductor alloy acquired through epitaxial growth has better quality and more stable performance, the graphene insertion layer has relatively high electron mobility, resistance of the metal-semiconductor alloy layer acquired through epitaxial growth and contact resistance of the semiconductor substrate and the metal-semiconductor alloy layer can be effectively reduced, and thereby electrical performance is improved.

Description

technical field [0001] The invention relates to the field of material preparation, in particular to a method for preparing a metal-semiconductor alloy by using a controllable defect graphene intercalation layer. Background technique [0002] In the prior art, when the metal thin film layer is directly grown on the surface of the semiconductor substrate, the contact characteristics of the interface between the grown metal thin film layer and the semiconductor substrate are relatively poor, and the quality and stability of the grown metal thin film layer are not good. . Such as figure 1 as shown, figure 1 It is the TEM image of the sample obtained after annealing at 400°C for 30s after directly forming a Ni metal layer on the surface of the Ge substrate. figure 1 It can be seen that both the surface of the NiGe thin film layer and the interface between the NiGe thin film layer and the Ge substrate are uneven and have uneven thickness. [0003] In order to solve the above p...

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Application Information

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IPC IPC(8): H01L21/02
Inventor 张波孟骁然俞文杰狄增峰张苗
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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