Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Ge-based solid-state plasma PiN diode and preparation method therefor

A plasma and diode technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of large injection dose and energy, uneven doping concentration, affecting the carrier concentration of pin diodes, etc. Improved breakdown voltage and enhanced controllability

Active Publication Date: 2017-05-31
XIDIAN UNIV
View PDF3 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] At present, the materials used in pin diodes used in plasma reconfigurable antennas at home and abroad are all bulk silicon materials. This material has the problem of low carrier mobility in the intrinsic region, which affects the carrier concentration in the intrinsic region of the pin diode. Affect its solid-state plasma concentration; and the P region and N region of this structure are mostly formed by implantation process, which requires a large implant dose and energy, high requirements on equipment, and is incompatible with existing processes; and the diffusion process, Although the junction depth is deep, but at the same time, the area of ​​the P region and the N region is large, the integration degree is low, and the doping concentration is uneven, which affects the electrical performance of the pin diode, resulting in poor controllability of the solid-state plasma concentration and distribution.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Ge-based solid-state plasma PiN diode and preparation method therefor
  • Ge-based solid-state plasma PiN diode and preparation method therefor
  • Ge-based solid-state plasma PiN diode and preparation method therefor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0057] See figure 1 , figure 1 It is a flowchart of a method for manufacturing a Ge-based solid-state plasma PiN diode according to an embodiment of the present invention. The method is suitable for preparing a GeOI-based lateral solid-state plasma PiN diode, and the GeOI lateral solid-state plasma PiN diode is mainly used for making a solid-state plasma PiN diode. antenna. The method comprises the steps of:

[0058] (a) selecting a GeOI substrate with a certain crystal orientation, and setting an isolation region in the GeOI substrate;

[0059] (b) etching the GeOI substrate to form a P-type trench and an N-type trench, and the depth of the P-type trench and the N-type trench is less than the thickness of the top layer Ge of the GeOI substrate;

[0060] (c) forming a first P-type active region and a first N-type active region by ion implantation in the P-type trench and the N-type trench;

[0061] (d) filling the P-type trench and the N-type trench, and using ion implanta...

Embodiment 2

[0101] See Figure 2a-Figure 2s , Figure 2a-Figure 2s It is a schematic diagram of a method for preparing a Ge-based solid-state plasma PiN diode according to an embodiment of the present invention. On the basis of the first embodiment above, to prepare a GeOI-based solid-state plasma with a channel length of 22 nm (the length of the solid-state plasma region is 100 microns) Taking a bulk PiN diode as an example to describe in detail, the specific steps are as follows:

[0102] Step 1, substrate material preparation steps:

[0103] (1a) if Figure 2a As shown, the (100) crystal orientation is selected, the doping type is p-type, and the doping concentration is 10 14 cm -3 A GeOI substrate sheet 101, the thickness of the top layer Ge is 50 μm;

[0104] (1b) if Figure 2b As shown, a first layer of SiO with a thickness of 40nm is deposited on a GeOI substrate by chemical vapor deposition (Chemical vapor deposition, CVD for short). 2 Layer 201; adopt the method of chemica...

Embodiment 3

[0133] Please refer to image 3 , image 3 It is a schematic diagram of a device structure of a Ge-based solid-state plasma PiN diode according to an embodiment of the present invention. The Ge-based solid-state plasma PiN diode adopts the above-mentioned figure 1 The preparation method shown is made, specifically, the Ge-based solid-state plasma PiN diode is prepared and formed on the GeOI substrate 301, and the P region 305, the N region 306 of the pin diode and the laterally located P region 305 and the N region The I regions between 306 are located in the top layer Ge302 of the GeOI substrate. Wherein, the pin diode can be isolated by STI deep trenches, that is, an isolation trench 303 is provided outside the P region 305 and the N region 306, and the depth of the isolation trench 303 is greater than or equal to the thickness of the top layer Ge302. In addition, the P region 305 and the N region 306 may respectively include a thin-layer P-type active region 307 and a th...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a Ge-based solid-state plasma PiN diode and a preparation method therefor. The preparation method comprises the steps of selecting a GeOI substrate of a certain crystal orientation, and setting an isolation region in the GeOI substrate; etching the GeOI substrate to form a P type trench and an N type trench, wherein the depths of the P type trench and the N type trench are smaller than the thickness of top layer Ge of the GeOI substrate; performing ion implantation in the P type trench and the N type trench to form a first P type active region and a first N type active region; filling the P type trench and the N type trench, and adopting ion implantation to form a second P type active region and a second N type active region in the top layer Ge of the GeOI substrate; and forming leads on the GeOI substrate to complete the preparation of the Ge-based solid-state plasma PiN diode. According to the embodiments, the high-performance Ge-based solid-state plasma PiN diode, which is applicable to formation of a solid-state plasma antenna, can be prepared and provided through a deep trench isolation technology and an ion implantation process.

Description

technical field [0001] The invention relates to the technical field of semiconductor device manufacturing, in particular to a Ge-based solid-state plasma PiN diode and a preparation method thereof. Background technique [0002] At present, the materials used in pin diodes used in plasma reconfigurable antennas at home and abroad are all bulk silicon materials. This material has the problem of low carrier mobility in the intrinsic region, which affects the carrier concentration in the intrinsic region of the pin diode. Affect its solid-state plasma concentration; and the P region and N region of this structure are mostly formed by implantation process, which requires a large implant dose and energy, high requirements on equipment, and is incompatible with existing processes; and the diffusion process, Although the junction depth is deep, the area of ​​the P region and the N region is large, the integration degree is low, and the doping concentration is uneven, which affects t...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L29/868H01L21/329
CPCH01L29/6609H01L29/868
Inventor 胡辉勇苏汉王策张鹤鸣王斌舒斌宋建军宣荣喜朱翔宇
Owner XIDIAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products