A kind of semiconductor device and its preparation method, electronic device

Abstract

The invention relates to a semiconductor device and a preparation method thereof, and an electronic apparatus. The method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate includes an NMOS region and a PMOS region, and a gate material layer is formed on the NMOS region and the PMOS region; performing first-type pre-doped ion implantation on the gate material layer above the NMOS region; performing high-temperature annealing on the NMOS region to evenly disperse pre-doped ions in the gate material layer above the NMOS region; and performing second-type pre-doped ion implantation different from the first-type pre-doped ion implantation on the gate material layer above the PMOS region. Pre-doped ions in the PMOS region can be prevented from diffusing into the NMOS region. The threshold voltage is more stable. The performance and yield of the semiconductor device are improved.

Description

technical field [0001] The present invention relates to the field of semiconductors, in particular, the present invention relates to a semiconductor device, a preparation method thereof, and an electronic device. Background technique [0002] With the continuous development of integrated circuit technology, more devices will be integrated on the chip, and the chip will also have faster speed. Driven by these requirements, the geometric size of devices will continue to shrink, and new materials, new technologies and new manufacturing processes will be continuously used in the chip manufacturing process. At present, the manufacturing process of semiconductor devices is gradually mature. [0003] With the continuous reduction of the size of semiconductor devices, more challenges are brought to the device preparation. At present, the preparation method of transistors in semiconductor devices is usually to form NMOS and PMOS gate material layers first, and then perform pre-doped...

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Problems solved by technology

However, defects in the outline of the NMOS gate structure usually occur in the device prepared by the method, for example, a defect appears on the top of the gate structure, forming a gap

[0004] By analyzing the defect, it is found that the cause of the structure is due to the implantation of P ions to the NMOS before etching. The current solution is usually to perform rapid thermal annealing after the NMOS pre-doped ion implantation to The phosphorus doped in the NMOS is diffused to the inside, but the method will cause the B doped in the PMOS to quickly diffuse to the NMOS, so some regions may be shared between the NMOS and the PMOS, thereby causing the threshold voltage of the semiconductor device to occur. degradation

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