Formation method for semiconductor structure

Abstract

Disclosed is a formation method for a semiconductor structure. The formation method comprises the steps of providing a semiconductor substrate; forming a plurality of fin parts, wherein a mask layer is arranged on the top arts of the fin parts, and first grooves and second grooves are formed between adjacent fin parts; forming an isolating layer in the first grooves and the second grooves; removing the mask layer to form a first dielectric layer and a second dielectric layer which cover the isolating layer and the fin parts; forming a patterned mask layer with openings on the surface of the second dielectric layer; performing ion implantation on the second dielectric layer along the openings; removing the patterned mask layer and performing annealing treatment to form a doping layer in the second dielectric layer, wherein the etching rate of the doping layer is less than that of the second dielectric layer; removing the second dielectric layer and a part of the doping layer of certain thickness; etching the first dielectric layer and remaining a part of the first dielectric layer of certain thickness; and etching the isolating layer to reduce the height, outside the second grooves, of the isolating layer. By virtue of the formation method, the non-etched isolating layer is formed, and a pseudo gate is formed on the surface of the non-etched isolating layer, so that performance of a to-be-formed transistor can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor structure. Background technique [0002] With the continuous development of semiconductor process technology, the process node is gradually reduced, and the gate-last (gate-last) process has been widely used to obtain an ideal threshold voltage and improve device performance. However, when the feature size (CD, Critical Dimension) of the device is further reduced, even if the gate-last process is adopted, the structure of the conventional MOS field effect transistor can no longer meet the requirements for device performance, and the fin field effect transistor (Fin FET) as Substitution of conventional devices has received extensive attention. [0003] In order to further improve the performance of fin field effect transistors, stress engineering is introduced into the transistor manufacturing process. After the source and drain grooves...

AI Technical Summary

Problems solved by technology

In the process of forming the polysilicon gates 21 across the fins 10, in order to improve the pattern uniformity of the polysilicon gates 21, shallow trench isolation between adjacent fins 10 arranged along the length direction of the fins 10 is usually performed. A dummy polysilicon gate 22 is formed on the surface of the structure 20. Since the surface of the shallow trench isolation structure 20 is lower than the top surface of the fin 10, the bottom of the dummy polysilicon gate 22 is also lower than the top surface of the fin 10, causing the dummy gate 22 There is a gap between the fin and the fin 10. During the process of forming the source and drain grooves in the fins 10 located on both sides of the polysilicon gate 21, it is easy to cause the morphology of the source and drain grooves to be affected, so that in the source and drain grooves The stress effect of the stress layer 11 filled inside becomes worse, and the stress layer 11 is also prone to bridging with the dummy polysilicon gate 22, which affects the performance of the formed fin field effect transistor

[0005] The performance of the fin field effect transistor formed by the existing technology needs to be further improved

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