Thin film transistor, fabrication method thereof, array substrate and display device

Abstract

The embodiment of the invention provides a thin film transistor, a fabrication method thereof, an array substrate and a display device in technical field of display, which can be used for improving ion injection efficiency of a source-drain and reducing the contact resistance between the source-drain and an active layer. The thin film transistor comprises a source, a drain, a gate, a gate insulation layer and an active layer, wherein the source, the drain and the gate are arranged on the substrate, and the active layer comprises poly-silicon, the source, the drain and the gate are arranged on the active layer, at least one through hole is formed in a contact region of the source and / or the drain and the active layer, and ions are doped into a region, corresponding to the through hole, of the active layer.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a thin film transistor, a manufacturing method, an array substrate, and a display device. Background technique [0002] With the development of display technology, the requirements for electron mobility of the thin film transistor (Thin Film Transistor, TFT) semiconductor layer are higher and higher. LTPS TFT has high mobility, can be prepared at relatively low temperature (below 600°C), flexible substrate selection, and low manufacturing cost. Therefore, it has been widely used in electronic products such as computers and mobile phones. various electronic displays. [0003] Such as figure 1 As shown, taking a P-type LTPS TFT device as an example, the LTPS TFT includes an active layer (p-Si) 101 formed on a substrate 10, a source 102, a drain 103, a gate insulating layer 105 and a gate Pole 104, in order to reduce the electric field of source 102, drain 103 and channel region...

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Problems solved by technology

[0004] However, in the above p + During the ion implantation process, the source 102 and the drain 103 will p + The implantation and diffusion of ions produces a certain hindering effect, which leads to p + The implantation efficiency of ions is low, so that the contact resistance between the source electrode 102 and the drain electrode 103 and the active layer (p-Si) 101 is still relatively large

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