Semiconductor memory device and manufacturing method thereof

Abstract

The invention provides a semiconductor memory device and a manufacturing method thereof. The manufacturing method of the semiconductor memory device includes the steps: forming an active region, vertically interlaced word lines and bit lines, and first and second insulating layers on a semiconductor substrate, wherein isolation materials are filled among the bit lines; forming a contact window and gaps in the first and second insulating layers through etching; filling the contact window and the gaps with conductive materials, and etching back the conductive materials to enable the conductive materials to be lower than the first insulating layer; and depositing the insulating materials and etching to remove the insulating materials at the middle part totally so as to form a contact pad window for a capacitor and maintain part of the insulating materials at two sides to form a contact pad side wall insulating layer. The manufacturing method of the semiconductor memory device manufactures a self-aligning three dimensional contact pad structure through photoetching and plasma etching technology, enables the word line and bit line array to joint with the capacitor array, and can realize connecting contact between hexagonal closest packing capacitor array and a tetragonal word line and bit line array, without increasing a rewiring layer, and can manufacturing the contact pad side wall insulating layer to improve the insulating effect.

Description

technical field

[0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a semiconductor storage device capable of realizing contact between a quadrangular array and a hexagonal array without adding a rewiring layer and a manufacturing method thereof. Background technique

[0002] Dynamic Random Access Memory (DRAM for short) is a semiconductor storage device commonly used in computers, and is composed of many repeated storage units. Each memory cell generally includes a capacitor 10 and a transistor 11; the gate of the transistor 11 is connected to the word line 13, the drain is connected to the bit line 12, and the source is connected to the capacitor 10; the voltage signal on the word line 13 can control the transistor 11 Open or close, and then read the data information stored in the capacitor 10 through the bit line 12, or write the data information into the capacitor 10 through the bit line 12 for storage, su...

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