A kind of bcd device and its manufacturing method

A manufacturing method and device technology, applied in the field of BCD devices and their manufacturing, can solve the problems of size reduction, cost increase, unfavorable cost savings, etc., and achieve the effects of increasing the number, reducing device loss, and improving competitiveness.

Inactive Publication Date: 2019-12-27
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this method will add a mask, which will increase the cost, which is not conducive to the cost saving of mass production. How to make BCD devices adapt to the reduction of device size without adding additional versions is an important task.

Method used

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  • A kind of bcd device and its manufacturing method
  • A kind of bcd device and its manufacturing method
  • A kind of bcd device and its manufacturing method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0039] Figure 4 Shown is a schematic diagram of the structure of a BCD device of the present invention, its cell structure includes a substrate 1, a first epitaxial layer 2, a second epitaxial layer 21, a first P isolation 311, a second P isolation 312, and a third P isolation 313, the first P well 31, the third P well 33, the fourth P well 34, the DMOS source P-type heavily doped region 310, the third P-type heavily doped region 37, and the fourth P-type heavily doped region 38 , the fifth P-type heavily doped region 39, the DMOS source N-type heavily doped region 4, the DMOS drain N-type heavily doped region 41, the second N-type heavily doped region 43, the third N-type heavily doped region Region 44, the fourth N-type heavily doped region 45, the fifth N-type heavily doped region 46, the DMOS source electrode 5, the contact electrode 51 of the first P well 31, the DMOS gate electrode 6, the PMOS gate electrode 62, the NMOS gate electrode Electrode 63, PMOS source electro...

Embodiment 2

[0053] like image 3 As shown, this embodiment is basically the same as Embodiment 1, and the main difference is that the BCD device further includes a P Type doped region 314 , the upper surface of which is tangent to the upper surface of the second epitaxial layer 21 .

[0054] The manufacturing method of the above-mentioned BCD device is basically the same as the manufacturing method in Embodiment 1, the difference is that after the second epitaxial layer 21 is grown, P-type impurity ions are implanted to form a P-type doped region 314, so that its upper surface is in contact with the second epitaxial layer 21. The upper surface of the epitaxial layer 21 is tangential.

Embodiment 3

[0056] like Figure 5 As shown, this embodiment is basically the same as Embodiment 2, the main difference is that the P-type doped region 314 arranged between the first P well 31 and the N-type heavily doped region 41 of the DMOS drain, on which The surface is not tangent to the upper surface of the second epitaxial layer 21 .

[0057] The manufacturing method of the above-mentioned BCD device is basically the same as the manufacturing method in Example 1, the difference is that: P-type impurity ion implantation is performed before the growth of the second epitaxial layer 21 to form a P-type doped region 314, so that its upper surface is not in contact with the second epitaxial layer 21. The upper surfaces of the two epitaxial layers 21 are tangent to each other.

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Abstract

The invention provides a BCD device and a manufacturing method thereof. The cell structure includes a substrate, an epitaxial layer, a P isolation, a P well, a P-type heavily doped region, an N-type heavily doped region, a DMOS source electrode, a first P Well contact electrodes, DMOS gate electrodes, PMOS gate electrodes, NMOS gate electrodes, source electrodes, drain electrodes, BJT base electrodes, BJT emitter electrodes, BJT collector electrodes; the present invention can reduce the mask of the Nwell region in the BCD process version, which is conducive to reducing the cost of mass-produced products and improving the competitiveness of products; the concentration of the epitaxial layer used to act as the Nwell region is increased, so that the number of carriers when the DMOS device is on increases, and the specific on-resistance of the DMOS is further reduced. Reduce device loss and improve device performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor power devices, in particular to a BCD device and a manufacturing method thereof. Background technique [0002] Power integrated circuits integrate high-voltage power devices, control circuits, peripheral interface circuits, and protection circuits on the same chip. As a bridge between the signal processing part and the execution part of the system, it has a very wide range of applications. Power integration technology is a means to realize power integrated circuits, which need to achieve high and low voltage compatibility, high performance, high efficiency and high reliability in a limited chip area. Before the mid-1980s, power integrated circuits were mainly manufactured by a bipolar process. However, with the continuous improvement of the functional requirements for the control part, the power consumption and area of ​​the integrated circuit became larger and larger. Therefore, it is possi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/06H01L21/822
CPCH01L21/822H01L27/0617
Inventor 乔明詹珍雅余洋梁龙飞王睿迪张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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