Cell array calculation system

Abstract

A cell array calculation system comprises an internal control CPU (Central Processing Unit), a cell array, a cell array bus, a bus controller, an external interface, a storage interface and at least one nonvolatile memory which adopts integrated reading and writing, wherein the cell array is a two-dimensional or three-dimensional array formed by more than one cells with calculation and storage functions; each cell includes a microprocessor and the nonvolatile memory; each cell stores a respective position in the cell array as an ID (Identity) so as to be read by software or hardware in the cell; the internal control CPU controls the storage interface, manages storage data and communicates with each cell in the cell array through the cell array bus, and distributes resources in the cell to complete a calculation task; the bus controller coordinates the control power of each main apparatus for the cell array bus. According to the cell array calculation system, communication bottlenecks among the CPU, an internal memory and storage can be overcome, the power consumption of a calculation system is greatly reduced, the processing speed is enhanced, the storage capability of large-scale data is expanded and the overall performance of the system is improved.

Description

technical field [0001] The invention relates to the technical field of computers and computer applications, in particular to a cell array computing system. Background technique [0002] Generally speaking, a computer mainly includes three core parts: a central processing unit (CPU, Central Processing Unit), memory and storage. [0003] Through the unremitting efforts of some of the world's top companies, the CPU has evolved into an extremely complex semiconductor chip. The number of MOS tubes inside the top CPU core can exceed 100 million. The current industry trend is that it is difficult to increase the operating frequency of the CPU due to power consumption constraints. It is also difficult to improve the operating efficiency of the already extremely complex modern CPU. New CPU products are increasingly evolving towards multi-core. [0004] In terms of memory, the current dominant technology is Dynamic Random Access Memory (DRAM, Dynamic Random Access Memory) technolo...

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Problems solved by technology

[0010] Therefore, due to the communication bottleneck between the CPU, memory and storage, the computer architecture in the prior art seriously reduces the data processing speed of the computing system and increases the power consumption of the computing system, thus affecting the overall performance of the system

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