Fabrication method of semiconductor device, semiconductor device and electronic device

Abstract

The invention provides a fabrication method of a semiconductor device. The fabrication method comprises the steps of providing a semiconductor substrate, wherein a first silicon fin structure and a second silicon fin structure are at least formed on the semiconductor substrate; forming silicon germanium layers at two sides of the first silicon fin structure and the second silicon fin structure; injecting germanium into the silicon germanium layers at the two sides of the second silicon fin structure to improve germanium concentration of the silicon germanium layers; and executing a SiGe concentration process so that the first silicon fin structure and the second silicon fin structure are converted to a first silicon germanium fin structure and a second silicon germanium fin structure, wherein the germanium concentration of the second silicon germanium fin structure is larger than that of the first silicon germanium fin structure. With the fabrication method of the semiconductor device, proposed by the invention, the silicon germanium fin structures with different germanium concentration can be formed on the semiconductor substrate, so that electron and hole migration capability in the fin structures can be improved, and the performance of the semiconductor device is improved.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device, a semiconductor device and an electronic device. Background technique [0002] With the development of semiconductor technology, the geometric size of the metal-oxide-semiconductor field-effect transistor (MOSFET for short), the main device in integrated circuits, especially VLSI, has been shrinking, and the feature size of semiconductor devices has been reduced to the nanometer level. . The process using a silicon dioxide (SiO2) layer as a gate dielectric has reached the limit of its physical and electrical characteristics, and the silicon dioxide layer in a 65nm process transistor has shrunk to a thickness of 5 oxygen atoms. As an insulator between the gate and the underlying layer, the silicon dioxide layer cannot be shrunk any further without leakage currents that would prevent the transistor from functioning p...

AI Technical Summary

Problems solved by technology

As an insulator blocking the gate and the underlying layer, the silicon dioxide layer can no longer be shrunk further, otherwise the leakage current will prevent the transistor from working properly.

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