A method for forming a channel layer in a 3d NAND device and a wafer box structure
A channel layer and wafer box technology, which is applied in the manufacture of semiconductor devices, electric solid devices, semiconductor/solid devices, etc., can solve the problems of large channel resistance and affect the overall performance of the device, so as to reduce channel resistance and suppress Natural oxidation, performance-enhancing effect
Active Publication Date: 2019-12-13
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology
[0004] In the traditional method of forming a polysilicon channel layer, the channel resistance is relatively large, which affects the overall performance of the device
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[0029] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.
[0030] First of all, in the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can Similar extensions are made below, so the present invention is not limited by the specific embodiments disclosed below.
[0031] Secondly, the present invention is described in detail in combination with schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagra...
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Abstract
Embodiments of the present invention provide a method for forming a channel layer in a 3D NAND device. The method includes: providing a substrate on which a stacked layer, a channel hole in the stacked layer, and the channel are formed. a charge trapping layer on the inner wall of the hole, the stacked layer is alternately stacked by a silicon nitride layer and a silicon oxide layer, a first polysilicon layer is formed on the side wall of the channel hole, and the first polysilicon layer is formed on the side wall of the channel hole. The substrate of the crystalline silicon layer is placed in an inert gas environment or a nitrogen environment, and a second polysilicon layer is formed in the channel hole. In this method, after forming the first polysilicon layer and before forming the second polysilicon layer, the substrate is placed in an inert gas or nitrogen environment. In this way, the growth of the second polysilicon layer can be effectively suppressed. During the waiting process, the natural oxidation of the first polysilicon layer reduces the proportion of silicon oxide in the channel layer, thereby reducing the channel resistance and improving the performance of the device.
Description
technical field [0001] The invention relates to the field of semiconductors, in particular to a method for forming a channel layer in a 3D NAND device and a wafer box structure. Background technique [0002] With the continuous advancement of informatization, people have higher requirements for information storage. Flash memory is a long-life non-volatile memory that has been widely used in electronic products. At present, the planar structure NAND flash memory is close to the limit of actual expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D structure NAND memory is proposed. [0003] In the 3D NAND memory structure, a stacked 3D NAND memory structure is realized by vertically stacking multiple layers of data storage units. When forming a 3D NAND memory, first, a stacked layer of a silicon nitride (SiN) layer and a silicon oxide (SiO2) layer is formed on the substrate; then, a channel hole (Channel hole) is formed in the ...
Claims
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IPC IPC(8): H01L27/11568H01L21/673H10B43/30
Inventor 王秉国王家友万先进吴关平吴俊郁赛华蒲浩
Owner YANGTZE MEMORY TECH CO LTD