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Semiconductor device, manufacturing method, and electronic device

A technology for electronic devices and semiconductors, used in semiconductor devices, semiconductor/solid-state device manufacturing, circuits, etc., and can solve the problems of inconsistent epitaxial stress layer contours, reduced device performance, and inaccurate alignment.

Active Publication Date: 2020-10-02
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In addition, the design usually includes a plurality of dummy gates for critical dimension control, usually the dummy gates are set on the shallow trench isolation region formed by the SDB, in order to improve the performance of the FinFET device, usually The source and drain on both sides of the gate structure form an epitaxial stress layer. Since the height of the dummy gate on the shallow trench isolation structure is not consistent with the height of the gate on the fin, if alignment occurs during epitaxy Offset, alignment is not accurate enough, it is easy to cause the profile of the epitaxial stress layer to be inconsistent, reduce the performance of the device or even fail

Method used

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  • Semiconductor device, manufacturing method, and electronic device
  • Semiconductor device, manufacturing method, and electronic device
  • Semiconductor device, manufacturing method, and electronic device

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preparation example Construction

[0063] In order to solve the above-mentioned problems existing in the current technology, the invention provides a method for preparing a semiconductor device, the method comprising:

[0064] providing a semiconductor substrate on which striped fins are formed;

[0065] patterning the fin strips to form grooves in the fin strips, the grooves dividing the fin strips into fin structures spaced apart from each other;

[0066] depositing a layer of isolation material to fill the groove and cover the fin structure;

[0067] forming a liner layer on the layer of isolation material above the groove to cover the layer of isolation material above the groove;

[0068] Etching back the isolation material layer on both sides of the liner layer to expose part of the fin structure;

[0069] A gate structure is formed on the fin structure, and a dummy gate structure is formed on the liner layer.

[0070] Wherein, the method for forming the liner layer includes:

[0071] forming a first l...

Embodiment 1

[0077] The preparation method of the semiconductor device of the present invention is described in detail below with reference to the accompanying drawings, figure 1 Shows a flow chart of the fabrication process of the semiconductor device of the present invention; figure 2 It shows a schematic cross-sectional view of the structure obtained by implementing the method for manufacturing the semiconductor device of the present invention; image 3 It shows a schematic cross-sectional view of the structure obtained by implementing the method for manufacturing the semiconductor device of the present invention; Figure 4 It shows a schematic cross-sectional view of the structure obtained by implementing the method for manufacturing the semiconductor device of the present invention; Figure 5 It shows a schematic cross-sectional view of the structure obtained by implementing the method for manufacturing the semiconductor device of the present invention; Image 6 It shows a schemati...

Embodiment 2

[0144] The present invention also provides a semiconductor device, the semiconductor device comprising:

[0145] semiconductor substrate;

[0146] a plurality of fin structures located on the semiconductor substrate and separated from each other by grooves;

[0147] a layer of isolation material, filled in the groove;

[0148] a gate structure located above the fin structure;

[0149] A dummy gate structure is located above the isolation material layer, wherein the height of the isolation material layer below the dummy gate structure is equal to or greater than the height of the fin structure.

[0150] Wherein, a liner layer is formed on the isolation material layer under the dummy gate structure.

[0151] Wherein, the height of the isolation material layer in the groove on both sides of the dummy gate structure is smaller than the height of the fin structure.

[0152] Wherein, the semiconductor device includes a semiconductor substrate 201, and the semiconductor substrate...

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PUM

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Abstract

The invention relates to a semiconductor device, a preparing method thereof and an electronic device. The method comprises the steps of providing a semiconductor substrate and forming a strip-shaped fin on the semiconductor substrate; patterning the strip-shaped fin to form a groove in the strip-shaped fin, wherein the groove divides the strip-shaped fin into fin structures which are spaced; depositing separation material layers to fill the groove and cover the fin structures; forming a lining layer on the separation material layers located above the groove to cover the separation material layer above the groove; re-etching the separation material layers at the two sides of the lining layer to expose part of the fin structures; forming grid structures on the fin structures, and meanwhile,forming a virtual grid structure on the lining layer. According to the method, the problem that the virtual grid and the grid structure are inconsistent in depth is solved, by improving the device, the performance is further improved, and the yield is further increased.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a preparation method, and an electronic device. Background technique [0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. At present, due to the demand for high device density, high performance, and low cost, the semiconductor industry has advanced to the nanotechnology process node, and the fabrication of semiconductor devices is limited by various physical limits. [0003] As the dimensions of CMOS devices continue to shrink, manufacturing and design challenges have prompted the development of three-dimensional designs such as Fin Field Effect Transistors (FinFETs). Compared with the existing planar transistors, FinFET is an advanced semiconductor device for 20nm and below pr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/78
CPCH01L29/66795H01L29/785
Inventor 赵海毛刚王青鹏
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP