Fan-out wafer-level chip packaging structure and method

A wafer-level chip and packaging structure technology, which is applied in the direction of electrical components, electric solid devices, circuits, etc., can solve the problems of difficult preparation and high production cost of fan-out wafer-level chip packaging structure, and achieve improved heat dissipation performance, The preparation difficulty is small and the effect of improving the positioning accuracy

Active Publication Date: 2018-04-20
NAT CENT FOR ADVANCED PACKAGING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] Therefore, the technical problem to be solved by the present invention is to solve the problem that the preparation of the electromagnetic shielding structure in the fan-out wafer-level chip packaging structure is relatively difficult, and the production cost of the fan-out wafer-level chip packaging structure is relatively high.

Method used

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  • Fan-out wafer-level chip packaging structure and method

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Embodiment 1

[0032] This embodiment provides a fan-out wafer level chip packaging structure, such as figure 1 As shown, it includes: conductive layer 1, a groove for setting chip 2 is formed on conductive layer 1; conductive layer 1 is arranged on substrate 3; insulating layer 4 is arranged between conductive layer 1 and substrate 3 for filling The gap between the conductive layer 1 and the substrate 3; the package 5 is arranged on the upper surface of the conductive layer 1; the chip 2 is packaged in the package 5, and the pad of the chip 2 is exposed outside the package 5; the conductive column 6 is set In the package body 5 , one end is coupled to the conductive layer 1 , and the other end is exposed outside the package body 5 ; the conductive post 6 is connected to the ground wire. In a specific embodiment, the depth of the groove is smaller than the thickness of the chip 2, and the conductive layer 1 is aluminum, copper, aluminum alloy or copper alloy layer. Preferably, the thickness ...

Embodiment 2

[0040] This embodiment provides a fan-out wafer level chip packaging method, such as figure 2 As shown, including the following steps:

[0041] Step S1: providing a substrate, and disposing an insulating layer on the upper surface of the substrate. Such as image 3 As shown, in this embodiment, the insulating layer 4 may be provided by spray coating or spin coating. In a specific embodiment, the material of the substrate 3 is a material with good thermal conductivity such as silicon, silicon carbide, thermally conductive ceramics or metal, and the insulating layer 4 is a photosensitive material layer prepared by photosensitive polyimide or other photosensitive resins. Of course, it can also be a non-photosensitive material layer. Preferably, the thickness of the insulating layer 4 is 2-20um.

[0042] Step S2: forming grooves on the insulating layer. Such as Figure 4 As mentioned above, in a specific embodiment, when the insulating layer 4 is a photosensitive material la...

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Abstract

The present invention provides a fan-out wafer-level chip packaging structure and method. The fan-out wafer-level chip packaging structure comprises: a conducting layer, wherein one groove configuredto arrange one chip is formed on the conducting layer, and the conducting layer is arranged on a substrate; an insulation layer arranged between the conducting layer and the substrate and configured to fill a gap between the conducting layer and the substrate; a packaging body arranged at the upper surface of the conducting layer, wherein the chip is packaged in the packaging body, one bonding padof each chip is exposed out of the packaging body; a conducting column arranged in the packaging body, wherein one end of the conducting column is coupled to the conducting layer, the other end of the conducting column is exposed out of the packaging body, and the conducting column is connected with a ground wire. The chip is arranged in the groove on the conducting layer, and the conducting layer is connected with the ground wire through the conducting column to form an electromagnetic shielding structure located in the fan-out wafer-level chip packaging structure, and therefore, the possibility can be reduced that the chip is subjected to electromagnetic wave interference by devices in the packaging structure and external devices, the preparation difficulty is small and the production cost is low.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a fan-out wafer-level chip packaging structure and packaging method with an electromagnetic shielding structure. Background technique [0002] With the popularity of wireless electronic devices, the integration of radio frequency chips is getting higher and higher, and fan-out packaging technology is increasingly used in radio frequency chip packaging. As the number of radio-frequency devices in the package increases, the direct electromagnetic interference between devices and modules, modules and modules becomes more and more prominent. It is more and more important to implement electromagnetic shielding structures in the fan-out packaging process. The conventional method is to apply an electromagnetic shielding metal shell outside the package body after the package is completed, but the metal shell increases the cost of the package and increases the volume of th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/13H01L23/367H01L23/544H01L23/552H01L21/48
CPCH01L21/4871H01L23/13H01L23/3672H01L23/544H01L23/552H01L2224/12105H01L2224/73267H01L2924/15153
Inventor 姚大平
Owner NAT CENT FOR ADVANCED PACKAGING
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