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Semiconductor device, fabrication method thereof and electronic device

A manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve the problems of weak points in contact holes and easy formation of oxides, and reduce leakage current and reduce leakage current. Effect

Active Publication Date: 2018-05-04
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, due to the high aspect ratio, the bottom of the contact hole generally forms a tapered profile, and oxides are easy to form when filling the isolation material, resulting in a weak point in the final contact hole, which in turn causes leakage current

Method used

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  • Semiconductor device, fabrication method thereof and electronic device
  • Semiconductor device, fabrication method thereof and electronic device
  • Semiconductor device, fabrication method thereof and electronic device

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Embodiment 1

[0046] The following will refer to Figure 5A ~ Figure 5C A method for fabricating a semiconductor device according to an embodiment of the present invention will be described in detail. In this embodiment, the fabrication method of the semiconductor device of the present invention is described by taking the fabrication of the trench in the interlayer dielectric layer as an example.

[0047] First, if Figure 5A As shown, a semiconductor substrate 500 is provided, a device layer 501 is formed on the semiconductor substrate 500 , a trench 502 is formed in the device layer 501 , and a spacer 503 is formed on the surface of the trench 502 .

[0048] Wherein, the semiconductor substrate 500 can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and also includes multiple semiconductors composed of these semiconductors. The layer structure or the like may be silicon-on-insulator (SOI), silicon-on-ins...

Embodiment 2

[0057] The following will refer to Figure 6A ~ Figure 6I A method for fabricating a semiconductor device according to an embodiment of the present invention will be described in detail. In this embodiment, the manufacturing method of the semiconductor device of the present invention is described by taking the manufacturing of the contact hole of the NOR device as an example. For the layout of the NOR device see Figure 2A shown in Figure 6A to Figure 6I For simplicity, only the device bit line orientation is shown (i.e., Figure 2A and Figure 2B Partial cross-sectional view in x-direction).

[0058] First, if Figure 6A As shown, a semiconductor substrate 600 is provided, and the semiconductor substrate 600 includes at least a storage area, and an isolation structure 601 and an active area AA separated by the isolation structure 601 are formed in the semiconductor substrate 600 of the storage area. A liner layer 602 and an interlayer dielectric layer 603 surrounding t...

Embodiment 3

[0089] The present invention also provides a semiconductor device fabricated by the above method, such as Figure 6I As shown, the semiconductor device includes: a semiconductor substrate 600, the semiconductor substrate 600 includes at least a storage area, and an isolation structure 601 and an active area AA separated by the isolation structure are formed in the semiconductor lining of the storage area. , a gate stack and an interlayer dielectric layer 603 surrounding the gate stack are formed on the semiconductor substrate 600 of the storage region, and a source contact and a drain are formed in the interlayer dielectric layer. A pole contact 607, wherein the drain contact has a vertical profile.

[0090] The drain contact of the semiconductor device in this embodiment has a vertical section, and the leakage current is reduced.

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Abstract

The invention provides a semiconductor device, a fabrication method thereof and an electronic device. The fabrication method comprises the following steps of providing a semiconductor substrate, and forming a device structure on the semiconductor substrate; forming a gap wall on a surface of the device structure, wherein the total widths of the gap wall and the device structure at each position ina horizontal direction both are larger than the maximum width of the device structure; modifying a part, exceeding the maximum width of the device structure, of the gap wall in the horizontal direction; and removing the modified part of the gap wall so that the remaining gap wall and the device structure form a perpendicular vertical section. By the fabrication method, a contact of NOR can be formed by employing a reversely-rotating self-aligned-contact process, the contact has vertical section, and meanwhile, a weak point is prevented from existing in the contact to cause leakage current. The semiconductor device and the electronic device have similar advantages.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] With the development of semiconductor process technology, the size of the contact hole (contact) is getting smaller and smaller. For the technology node of 28nm and below, self-aligned-contact (self-aligned-contact, SAC for short) needs to be used. SAC process such as Figure 1A and Figure 1B As shown, a gate stack composed of a gate oxide layer 101, a gate 102 and a hard mask layer 103 is formed on a semiconductor substrate 100, and a spacer and an etch stop layer 104 are formed on the sidewalls of the gate stack. Then an interlayer dielectric layer 105 is formed, and then a photoresist layer 106 is formed on the interlayer dielectric layer 105. The photoresist layer 106 defines the pattern of the contact hole, and then the photoresist layer 106 is use...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L27/115H10B41/00H10B69/00
CPCH01L21/76897H10B41/00
Inventor 郑二虎
Owner SEMICON MFG INT (SHANGHAI) CORP
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