Process integration structure and method of flash memory

Abstract

The invention discloses a process integration structure of flash memory. The gate structure of the flash memory unit includes a stacked structure formed by a first gate oxide layer, a polysilicon floating gate, a second ONO layer and a polysilicon control gate; The plan view dimensions of the source region and the polysilicon floating gate are the same and self-aligned. Corresponding source regions and drain regions are respectively formed in the active regions on both sides of each polysilicon control gate, and the top of the drain region is connected to the bit line of the corresponding column through a contact hole; a third silicon oxide is sequentially formed on the surface of the polysilicon gate row layer and a fourth silicon nitride layer. The invention also discloses a flash memory process integration method. The device of the present invention covers the fourth silicon nitride layer on the surface of the polysilicon control gate, which can reduce the leakage between the drain region contact hole and the polysilicon control gate, thereby facilitating the reduction of device size, and at the same time can eliminate the problem introduced by silicon nitride on the surface of the polysilicon control gate. Stress defects and elimination of polysilicon gate surface defects in logic regions.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a process integration structure of a flash memory; the invention also relates to a process integration method of a flash memory. Background technique [0002] Flash memory has been widely used as the best choice for non-volatile memory applications due to its advantages of high density, low price, and electrical programmability and erasability. At present, flash memory cells are mainly implemented at the 65nm technology node. With the demand for large-capacity flash memory, the number of chips on each silicon wafer will be reduced by using the existing technology nodes. At the same time, the increasing maturity of new technology nodes also promotes the production of flash memory cells with high-node technologies. It means that the size of the flash memory unit needs to be reduced. The reduction of the active area width and channel length of the flash memory unit ...

AI Technical Summary

Problems solved by technology

[0004] The silicon nitride currently used directly covers the structure of the polysilicon gate, which can achieve a better protection mechanism for the flash memory cell area, but the stress of silicon nitride is relatively large, and it is directly in contact with polysilicon. After the subsequent process, it may cause nitriding. Separation of Silicon and Polysilicon

[0005] At the same time, for the logic area, when silicon nitride is removed, it may cause damage to the polysilicon surface

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