Semiconductor device and preparation method thereof, and electronic apparatus

Abstract

The invention relates to a semiconductor device and a preparation method thereof, and an electronic apparatus. The method comprises the following steps: providing a first wafer, wherein the first wafer has a first surface and a second surface, which are arranged to be opposite to each other, a first bonding ring is formed on the first surface, and a first scribe lane is formed on the edge of the first surface on the outer side of the first bonding ring; providing a second wafer, wherein a second bonding ring is formed on the surface of the second wafer; bonding the first bonding ring with thesecond bonding ring to bond the first wafer with the second wafer; thinning the second surface of the first wafer to expose the first scribe lane so as to expose a cutting channel area of the second wafer; and cutting the first wafer and the second wafer. The preparation method provided by the invention has the advantages of: 1. simplifying the cutting process (blind dicing and multiple alignmentoperations are omitted), reducing the cutting frequency, and effectively reducing the process cost.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a preparation method, and an electronic device. Background technique [0002] In the field of electronic consumption, multi-function devices are more and more popular among consumers. Compared with devices with simple functions, the production process of multi-function devices will be more complicated, such as the need to integrate multiple chips with different functions on the circuit board, so 3D integrated circuit (integrated circuit, IC) technology is defined, and 3D integrated circuit (integrated circuit, IC) is defined as a system-level integrated structure, where multiple chips are stacked in a vertical plane direction, thereby saving space. [0003] With the development of 3D IC technology, MEMS products are becoming more and more abundant, and some products still use traditional technology, adding some test patterns (test keys) in the scrib...

AI Technical Summary

Problems solved by technology

[0005] 1. There is no alignment mark after the upper and lower silicon wafers are thinned, and blind cutting is required on the edge of the silicon wafer, so as to expose the graphics and perform die saw alignment; at the same time, the cutting depth of the first knife Can not touch the graphics on the second surface, need to adjust the cutting depth of the first knife

These two actions will lose some die, and more experienced engineers are required to carry out

[0006] 2. Due to the large thickness, the distance from the edge of the first wafer is greater than or equal to 200um. Therefore, the first wafer needs to be cut twice to make the silicon wafer on the dicing road fall, but the dropped silicon wafer Relatively large, easy to hit the knife, causing the shaking of the cutting knife, resulting in chipping

[0007] 3. Since two silicon wafers are cut, there is a cavity in the middle, the risk of lateral chipping is relatively high, and it is difficult to observe. We can only infer the lateral chipping ( Lateralchipping), so as to determine whether the die saw has damaged the Al / Ge bonding ring (bonding ring), causing reliability issues (reliability issue)

[0008] Other methods in the current process when cutting MEMS products, due to the special product, is a closed space structure, the current practice: because the upper and lower wafers have no cutting alignment marks (mark), so the edge of the cap wafer (cap wafer) must be blind cut Expose the dicing groove (recipe-1); align the exposed dicing groove area and measure the height of the knife so that it cannot touch the second wafer pattern (touch wafer2pattern); cut the entire covering wafer after aligning again round (cap wafer (recipe-2)), but because the width of the first wafer from the edge is large, it is easy to damage the blade and produce chipping when cutting and falling; align and cut the fully exposed wafer Entire MEMS+CMOS wafer (wafer(recipe-3))

The entire process is extremely cumbersome and requires manual handling, which increases risks and burdens virtually, and the wafer (Si crack) is easy to damage the Al / Ge bonding ring during the dicing process

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