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SRAM device and its manufacturing method

A manufacturing method and device technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problems of SRAM device electrical performance to be improved, achieve superior structural performance, improve electrical parameter mismatch, and improve electrical performance effect

Active Publication Date: 2019-09-27
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the electrical performance of SRAM devices formed by the prior art needs to be improved

Method used

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  • SRAM device and its manufacturing method
  • SRAM device and its manufacturing method

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Embodiment Construction

[0033] It can be seen from the background art that the electrical performance of the SRAM device formed in the prior art needs to be improved.

[0034] Now combined with a SRAM device for analysis, refer to figure 1 , figure 1 It is a schematic top view of a SRAM device, the SRAM device includes a pull-up (PU, Pull Up) transistor, a pull-down (PD, Pull Down) transistor and a pass gate (PG, Pass Gate) transistor, wherein the first region 101 In order to form a region with a pull-up transistor, the second region 102 is a region where a pull-down transistor is formed, and the third region 103 is a region where a pass-gate transistor is formed. Generally, the pull-up transistor is a PMOS transistor, a pull-down transistor and a pass-gate transistor. For NMOS tube.

[0035] Taking the SRAM device as a FinFET device as an example, the first region 101 is adjacent to the second region 102, and the first region 101, the second region 102 and the third region 103 all have fins 105, a...

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Abstract

A SRAM device and its manufacturing method, the manufacturing method comprising: forming a gate dielectric layer on part of the substrate of the pull-up transistor region and the pull-down transistor region; forming a first work function layer on the gate dielectric layer; etching and removing the pull-down transistor The first work function layer in the region; the second work function layer is formed on the remaining first work function layer and the pull-down transistor region, and the material of the second work function layer is a P-type work function material; in the pull-up transistor region A diffusion barrier layer is formed on the sidewall of the remaining second work function layer and the sidewall of the remaining first work function layer; on the diffusion barrier layer, on the top of the second work function layer of the pull-up transistor region, and on the gate of the pull-down transistor region A third work function layer is formed on the dielectric layer, and the material of the third work function layer is an N-type work function material; a gate electrode layer is formed on the third work function layer. The invention improves the electrical parameter mismatch of the SRAM device and optimizes the electrical performance of the formed SRAM device.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to an SRAM device and a manufacturing method thereof. Background technique [0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three types: logic, memory and analog circuits, among which memory devices account for a considerable proportion of integrated circuit products. With the development of semiconductor technology, storage devices are more widely used, and the storage device and other device regions need to be formed on a chip at the same time to form an embedded semiconductor storage device. For example, to embed the storage device in the central processing unit, it is necessary to make the storage device compatible with the embedded central processing unit platform, and maintain the specifications and corresponding electrical performance of the original storage device. [0003] Generally, the memory devic...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11H01L29/49H01L21/8244
CPCH01L29/495H01L29/4966H10B10/12
Inventor 李勇
Owner SEMICON MFG INT (SHANGHAI) CORP
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