Conductor structure, capacitor array structure and preparation method

Abstract

The invention provides a conductor structure based on a polysilicon process, a capacitor array structure and a preparation method. The preparation method of the conductor structure comprises the stepsthat a substrate is provided, and a recess structure is formed in the substrate; a conductor filling structure is formed in the recess structure, and a material source which forms the conductor filling structure at least comprises a silicon source and a germanium source; and germanium atoms in the germanium source serve as crystal nucleuses for aggregating and growing silicon atoms in the siliconsource to increase the silicon crystal grain size in the conductor filling structure. According to the scheme provided by the invention, the method of manufacturing large-grain polycrystalline silicon is proposed; the crystal nucleus element for aggregating and growing silicon crystal grains is introduced, such as germanium, so that silicon atoms are aggregated to increase the crystal grain size;increasing the crystal grain size of polycrystalline silicon can reduce the influence of grain boundary traps on carriers and further increases the conductivity; a protective layer is arranged to prevent the influence of germanium in the conductor filling structure on the process; and the conductor filling structure and other structural layers are effectively connected, which further improves theelectrical properties of the conductor filling structure.

Description

technical field [0001] The invention belongs to the field of semiconductor devices and manufacturing, and in particular relates to a conductor structure based on a polysilicon process, a capacitor array structure and a preparation method. Background technique [0002] Dynamic Random Access Memory (DRAM for short) is a semiconductor storage device commonly used in computers, and is composed of many repeated storage units. Each memory cell usually includes a capacitor and a transistor; the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor; the voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage. At present, in the DRAM process below 20nm, the DRAM adopts a stacked capacitor structure, and its ca...

AI Technical Summary

Problems solved by technology

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a conductor structure based on polysilicon process, a capacitor array structure and their respective preparation methods, which are used to solve the limitations of improving polysilicon crystal grain size and polysilicon crystallization in the prior art. Problems such as increased conductivity caused by too small particle size

Images