GaN-based HEMT device
A device, N-type technology, applied in the field of GaN-based HEMT devices, which can solve problems such as failure of GaN devices, uneven and smooth metal diffusion morphology, leakage and penetration, etc.
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Embodiment 1
[0031] figure 1 A schematic cross-sectional view of a GaN-based HEMT device provided by this embodiment is shown. Reference figure 1 As shown, the GaN-based HEMT device includes a substrate 101, a buffer layer 102, a GaN channel layer 103, a first barrier layer 104, a second barrier layer 105, a dielectric passivation layer, and a dielectric passivation layer stacked sequentially from bottom to top. It includes a gate electrode 108, a drain electrode 109, and a source electrode 110. Wherein, the dielectric passivation layer is composed of a SiN dielectric layer 106 of equal width formed on the second barrier layer 105, and the second barrier layer 105 and the SiN dielectric layer 106 are formed to extend to the first barrier layer. A window on the upper surface of the layer 104, in which a gate metal is deposited to form a gate electrode 108. The gate electrode 108 is formed on the upper surface of the first barrier layer 104 and the upper part thereof covers the upper surface ...
Embodiment 2
[0041] figure 2 A schematic cross-sectional view of another GaN-based HEMT device provided by this embodiment is shown. Reference figure 2 As shown, the difference between this embodiment and Embodiment 1 lies in:
[0042] The dielectric passivation layer has a two-layer structure composed of a first dielectric layer formed on the second barrier layer 105 and a second dielectric layer formed on the first dielectric layer. The first dielectric layer is SiN dielectric layer 106, and the second dielectric layer is SiO 2 Medium layer 107. The second barrier layer 105, SiN dielectric layer 106, SiO 2 The width of the dielectric layer 107 is equal, and the gate electrode 108 is formed on the second barrier layer 105, SiN dielectric layer 106, SiO 2 In the dielectric layer 107 and its upper part is covered with SiO 2 The upper surface of the dielectric layer 107. The edge 111a of the N-type ion implantation region 111 on the side close to the gate electrode 108 and the SiN dielectric...
Embodiment 3
[0045] image 3 A schematic cross-sectional view of another GaN-based HEMT device provided in this embodiment is shown. Reference image 3 As shown, the difference between this embodiment and Embodiment 1 lies in:
[0046] The dielectric passivation layer has a two-layer structure composed of a first dielectric layer and a second dielectric layer. The first dielectric layer is SiN dielectric layer 106, and the second dielectric layer is SiO 2 Medium layer 107. The SiN dielectric layer 106 is formed on the upper surface of the second barrier layer 105, and the widths of the second barrier layer 105 and the SiN dielectric layer 106 are equal; SiO 2 The dielectric layer 107 is formed on the upper surface of the SiN dielectric layer 106 and the side surfaces of the SiN dielectric layer 106 and the second barrier layer 105. SiO 2 The width of the dielectric layer 107 is greater than the width of the SiN dielectric layer 106 and the second barrier layer 105. The gate electrode 108 i...
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